In vhdl, I know how to code a start timer behavorially. However, if I have to implement such a counter to start based on a trigger, how could I implement such a counter?
My trigger is another signal that will be active for only one clock cycle.
I'm breaking my head trying to think of how this is done. I could add logic to check if my trigger is active high (1 and-ed to my signal) but then it will go inactive after 1 clock cycle.
I've seen counters with enable but I want to count and stay counting no matter what.
Best Answer
As long as you can ensure that the trigger signal is high for at least one full clock cycle, you can do something as simple as this:
circuit built with www.falstad.com
The trigger doesn't need to be synchronous with the clock, but it does need to be held high for at least a full clock cycle. Otherwise, the trigger may not be registered by the flip-flop (DFF).
You can also add a reset to the DFF if desired, to disable the
enableand allow the circuit to be retrigger.If you're concerned about metastability, just add a second DFF stage.