Electronic – How to make a register in VHDL remember

fpgaregistervhdl

I was given the assignment to implement an 18-bit register in VHDL. I used an example from the book "Free Range VHDL" recommended to me earlier. Here's what I got:

library IEEE;
use IEEE.std_logic_1164.all;

entity reg18 is
    port ( REG_IN  :  in std_logic_vector(17 downto 0);
           LD,CLK  :  in std_logic;
           REG_OUT : out std_logic_vector(17 downto 0));
end reg18;

architecture reg18 of reg18 is
begin
    reg: process(CLK)
    begin
        if (rising_edge(CLK)) then
            if (LD = '1') then
                REG_OUT <= REG_IN;
            end if;
        end if;
    end process;
end reg18;

However, the mentor argued that it doesn't remember the input and something with the VHDL signal must be done. Nevertheless, here's a citation from the same book:

If you have not speciﬁed what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By deﬁnition, if the input changes to an unspeciﬁed state, the output remains unchanged. In this case, the output associated with the previous set of input can be thought of as being remembered. It is this mechanism, as strange and interesting as it is, that is used to induce memory in the VHDL code.

Can you, please, explain to me how the mechanism of remembering in VHDL really works? Thank you in advance.

EDIT: By signal was meant the VHDL signal that is opposed to the variable. And yes, your comments confirm the citation.

Best Answer

One possibility is that your mentor is considering that signal declarations are needed to provide the "storage" for the register. Just as an example, they are declared in this document from Xilinx:

The flip-flops are not synthesized because of the signal declarations. It is the edge triggered part of the code you have shown that implies the flip-flops, regardless of the fact that they handle inputs and outputs directly.

As you can see, the synthesis of your code (using Vivado) correctly results in a series of d-flip-flops:

Additionally, take a look at this question and the 2 up-voted answers.

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

Electronic – Serial Adder vhdl design

z : out std_logic_vector(n - 1 downto 0)); The output must be std_logic, because it is a serial output

Also, you can use the + operator directly to the std_logic_vectors. Just add the "ieee.std_logic_signed" library So that you can write z_reg <= x+y;

if rising_edge(clk) then if clr = '1' then --clear all the registers, and flip flop

            c_reg <= '0';
            z_reg <= (others => '0');
        elsif load = '1' then
            z_reg <= x + y;

        else --execute sum       

            --full adder logic      
            z <=  z_reg(0);
            z_reg <= '0'& z_reg(n-1 downto 1);
        end if;
    end if;

Best Answer

Related Solutions

Electronic – Problem getting VHDL syntax correct

Electronic – Serial Adder vhdl design

Related Topic