Electronic – How to make Op Amp Gain Switch Solid state. (vs jumper)

digital potentiometergainoperational-amplifiersolid-state-relay

Existing op-amp circuit
How do I create a low-cost solid-state op-amp gain switch to replace a header and jumper? Header pins and jumpers are expensive parts to place, take up a lot of room and the jumper is a headache to manage in assembly. Also, this is part of a product and a user-selectable jumper represents a UI inconsistency; all the other circuit parameters are set in software.

About the circuit: This is a digitally controlled voltage signal generator used in part of an analog feedback control system. Bandwidth requirements are low (<20kHz). The basic circuit tests well. Currently a jumper selects the gain of the second-stage amp. The circuit range is normally +/-10V with no jumper and +/-5v when the jumper brings R7 in parallel with R5.

The jumper goes where U14 is currently shown. How do I replace that Jumper with something solid-state?

  • Back-to-back small discrete signal MOSFETs? Don’t all the below
    implement some kind of back-to-back switch tpology for low-resistance
    bi-directional control? Why can't I build one from discrete components?
    (Because I don't know how. This is where my design ability/experience breaks
    down
    .)
  • At first glance an inexpensive 1 channel analog switch (FSA4157)
    seemed like a good fit (U14) until I realized the switched voltage
    range of the inexpensive chips are limited to Vss-Vcc
    (0-5v).
  • A digital potentiometer would add variable gain control and eliminate
    R5, R6, R7. Again, it turns out the tiny, inexpensive chips
    (MCP4013) also have similar voltage range limitations.
  • A quick search of analog switches and digital potentiometers with
    expanded ranges yields impractical prices.
  • Solid state “relays” I’ve found are surprisingly bulky and/or
    expensive (CPC1017N). It appears these typically have an opto-isolators
    (which I don't need).

This question has been edited from the original post which was flagged as "off-topic" — probably because I discuss at length the cost reasons why some design options are already ruled out. I contend there is a very specific design question (which was adequately answered) and that cost considerations are not always the same thing as "shopping recommendations" (which are considered off-topic). In the real world, cost is almost always a principle consideration for making design decisions — especially with numerous otherwise feasible design options.

Best Answer

Circuit modified. sources commoned and R& D added. May well work without R3 - see below.
R3 value not shown but could be 10M or higher if environment allows.
R2 can be lower if desired.
Needs thinking but workable (I believe). It's the sort of circuit that can be made to work entirely reliably but which 'has things to think about along the way'.
The main point of unusualness is that the mode with two gates is "floating". R2 turns both FETs off when no external drive is applied.
My experience has been that applying external drive to the floating gate pair tends to cause them to assume the expected on state BUT there is no definite formal path to get there. Adding R3 allows the gates-node to be ground referenced but to float until driven. Once on, it works as expected.

Note: Almost all circuits are "designable". This one is too - but to be fully formally designed needs a few parts which in practice can be omitted. That does not mean that the end result need be unreliable - just that the factors at work that make it work with fewer parts than may be expected take more thinking about than usual.


Place a resistor in parallel with R6 and in series with 2 s 'jellybean" N channel MOSFETS in series opposed connection. ie
D1 ground
S1 S2 connected
G1 G2 connected D2 to R6b
Drive G1-G2 via a high = on, ground = off signal.
Note resistor biasing to 'persuade' floating node to be ground referenced.
Diode drive provides high or O/C drive.

Adjust R5 and R6a-R6b values to suit.
If R6 = say 12k then a MOSFET Rdson of 100 milliohms per FET = resistance error of +0.2 Ohm/12k ~= 0.002% - so temperature and device variations "not an issue".

Cost in modest volume manufacturing in China = $US0.01/MOSFET + assembly and PCB area costs.

The circuit utilises the fact that MOSFETs are 2 quadrant devices. Each device is on bidirectionally when gate is positive relative to source regardless of D-S polarity.
Two devices are required in series opposition due to body diodes which otherwise would provide reverse conduction when the FET was off.
For small amplitude signals where V_R6 was << 0.6V one might "get away with" a single MOSFET, but this is an imperfect solution as diodes still conduct (at 'exponentially' lower currents) at lower voltages.

schematic

simulate this circuit – Schematic created using CircuitLab