In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock):
always @(posedge clk_100Mhz_i)
begin
// Synchronizer chain... hopefully
clk4_del0 <= clk4_77_i; // SysClk from ext pin
clk4_del1 <= clk4_del0;
clk4_del2 <= clk4_del1;
end
// Used to clock internal regs
assign clock_4_77Mhz = clk4_del2;
// Sample
always @(posedge clock_4_77Mhz)
begin
timerIdx <= timerIdx +1;
end
Unfortunately I get the following warning:
Warning (332060): Node: X8255_top:x8255|clk4_del2 was determined to be a clock but was found without an associated clock assignment….
I also get a warning about an unconstrained clock. I tried to use what the Timing Analyzer suggested and added the fourth line to my .SDC:
# Constrain clock port clk_25MHz_i
create_clock -period "25.0 MHz" -name clk_25MHz [get_ports clk_25MHz_i]
create_clock -period "4.77 MHz" -name clk_4_77MHz [get_ports clk_4_77_i]
create_clock -name {X8255_top:x8255|clk4_del2} -period 210
without success.
What am I doing wrong?
Best Answer
Likely, it is because
clk4_del2
is not used as a clock (e.g. connected to a clock input of a DFF), but as an intermediate signal... you may even find it gets optimized-out (in your reports?) as it is a continuous assignment. Unless you use a primitive (clock buffer maybe) and tell the tool not to remove the buffer, and thus the buffer contributes to path delay (and it forces a "name change"), I don't think it will resolve as you intend.Alternatives, you probably realize already and are only asking because want to keep the RTL as-is, but jic:
If you were to replace your
clk_4_77MHz
clocked process withclk4_del2
you should find that the constraint resolves properly.... but, then you have the dangling net ofclk_4_77_MHz
(assuming it isn't used anywhere else) and that is kind of ugly.If you like your
clk_4_77MHz
(i.e. it is more descriptive), eliminate theclk4_del2
and replace the assignment:clk4_del2 <= clk4_del1
withclk_4_77MHz <= clk4_del1
.Either that, or just leave everything the way it is and remove the constraint for
clk4_del2
, and your intent, and the tool's interpretation of your intent, should remain the same.