Electronic – How to redirect/regenerate an input clock to an output pin in the FPGA design (Verilog)


I've got an ADC that requires me to send it 20 clock pulses when requesting to read data out of its internal register (after I've triggered it to read data from my sensor).

I was able to simulate this just fine in ModelSim but I'm new to Verilog and didn't realize that I would run into problems during synthesis when creating the pulse train like this:

reg [4:0] counter = 5'b10100;
parameter counter = 0;

always (posedge clk and negedge clk) 
   if (counter > 0)
       counter <= counter - 1;
       serial_out <= ~serial_out; 

I tried splitting this into 2 always blocks: one which sets serial_out to 1 on a posedge clk and another which sets serial_out to 0 during negedge clk, both checking if the counter is greater than 0. This is problematic because I'm attempting to drive counter in two places and get errors stating "can't resolve multiple constant driver for net counter .."

Perhaps there is a better way to do this?

I've seen some posts suggesting to double the clk frequency to read the data off of the posedge of the clock. This would work but I need to keep the clock at 30 MHz (can't go to 60 MHz for other reasons).

How would you suggest that I conditionally route/replicate 20 pulses of my always-on periodic 30 MHz input clock to an output pin?

Any help will be greatly appreciated.

Best Answer

I would suggest using an output DDR flip flop. How you implement that depends on what FPGA you're using. For Xilinx, it would be an ODDR or ODDR2 primitive. For Altera, it's ALTDDIO_OUT.