Electronic – How to setup PCB to correct for signal integrity issues after boards are made

I think you're on the right path, a couple of notes,

1) With a signal trace between two planes, the return current will split between the two planes, even if one of the planes is split. The return current cannot "see the future" and decide ahead of time which plane to return on. It will return above and below the trace until it sees the split at which point is says "oh crap!" and pays you back by possibly causing you to fail FCC testing. So you want to avoid running traces over plane splits even if another adjacent plane is not split. You can deal with splits with capacitors and such but this type of solution is less than ideal. I'd focus on always avoiding running a trace over a plane split on an adjacent plane.

2) Wide return paths on DC signals don't really matter.

3) You asked about two signal layers sharing the same plane. Usually, this is not a big deal if done properly. What many people do is use one of the layers as a "horizontal" signal layer and the other as a "vertical" signal layer so the return currents are orthogonal to each other. It is very common to route two signal layers for each plane, and use this horizontal/vertical technique. The most important thing to remember is to not change reference planes. Your setup could be a little tricky because going from the bottom layer to the 4th layer adds another return plane. More typical 6 layer boards are

1)ASignalHor 2)GND 3)ASignalVer 4)BSignalHor 5)POWER 6)BSignalVer

If you need smaller additional planes, like under the micro, these would usually be placed as an island on one of the signal layers. If you need to use more power planes, you might want to think about going to 10+ layers.

4) Plane spacing is important, and can have huge impact on performance, so you should specify this to the board house. If you take the example 6 layer stackup I mentioned above, spacing of .005 .005 .040 .005 .005 (instead of standard stackup with equal distance between layers) can make an order of magnitude improvement. It keeps the signal layers close to their reference plane (smaller loops).

I'd tend to ensure that the setup and hold times were OK and not worry too much about the edges you are seeing from a timing point of view.

I'd be more worried about the 2V overshoot BUT this may not be real. At that sort of edge timing it is very possible for your instrumentation to interact substantially with the system you are measuring. (Heisenberg would feel right at home :-) ). What are you measuring this with? If you have good practical experience in measuring 10 nS rise and fall times then these traces may be correct. If not then they may not. robe tip without sleeve right at signal point. Ground from probe tip to ground on IC nearest signal point and with connection length of about 0.00 mm :-). 1000 MHz probe. Tektronix, HP, Agilent. Others maybe :-).
You circuit doesn't have to look like this BUT this is an example of Jim William's scope connections at << 100 MHz.

AN47 Liner Technology - High Speed Amplifier techniques and see refs at end.

BUT

I would strongly consider making the system so it could not make signals which could damage your CPLD. Using Schottky diode clamps to either power supply rail would help ensure this. On each wire a reversed biased diode is connected from circuit to V+ and circuit to ground. When signals are inside the rails the diodes do not conduct. If the signal "rings" outside the "rails" then the diodes clamp the signals. This is a standard method and effective. In some cases you will get interactions between what the diodes do and what you are trying to do BUT if this happens it is probably an indication that you need to fix what you are doing.

Excellent related Analog Devices app note Switch and Multiplexer Design Considerations for Hostile Environments

Diagram below from the above - sampler only - see app note.

I believe the following advice is good enough [tm] but my experience in such areas is relatively limited and relatively long ago - others with more and more recent practical experience may wish to suggest alternatives.

• I'd also consider adding a small series drive resistor of the order of the lowest line impedance that you expect to drive.

• Passive pullup gives you relatively informal control over your driver - is there any reason not to use an active high/low drive - probably using a buffer IC. This is liable to be as or more compact, cheaper and more designable.

• You could consider a pullup/pulldown far end resistor termination to provide both ~~~ correct termination and correct mean level. eg 220r pullup and 33r pulldown or whatever.

References:

AN6039 - Board Layout Techniques for High-Performance Amplifiers

Analog Devices - HIGH SPEED HARDWARE DESIGN TECHNIQUES

Potential relevance to your circuit. Variable characteristic wiring loom drive makes this harder.

TI - High-Speed Amplifier PCB Layout Tips

Interesting - Review of Jim Williams: AN47 High Speed Amplifier Techniques