I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation primative, but Gowin provides no simulation resources that I know of. I would happily write code to infer the RAM if I completely understood the details to know I have it right. These buggers have some tricky behavior in the read after write situation. The "semi-dual port" mode only has one option for that, "normal" mode which seems to have a delay for turning around the direction of the write port to read. But semi-dual port has a write port and a separate read port (meaning the one port read mode is not used and the other port write mode is not used) so how can there be a limitation on the read when writing on a separate port??? I probably need to read the description again until it all sinks in.
Until then, is it customary for the FPGA vendor to supply a simulation library for their instantiated FPGA components?
Synth guide https://www.gowinsemi.com/upload/database_doc/762/document/5f7426a6bf224.pdf
B-SRAM & S-SRAM User Guide https://www.gowinsemi.com/upload/database_doc/1232/document/5f7befe0a7c86.pdf
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Best Answer
My opinion? Don't instantiate. Infer wherever you possibly can.
Find out how your synth tool infers BRAM and write memory that it can translate into BRAM. (It's just an array; you may need to clock the address and/or data to make it synchronous). Semi-dual port ... limitation on read may only apply when concurrently writing to the same address? Link to the datasheet if in doubt. There should also be a "synthesis style guide" to help.
Mock up a simple testcase and synth it to see if you get the usage you expect.