This article gives 2 main disadvantages:
- Variable frequency
- Requires ESR on the output cap
Is variable frequency a big of a deal? Why would synchronization matters for a converter?
And why are high ESR necessary for it to work? What I'm missing here?
I ask this because I've been working on a boost converter with hysteresis control as a Uni project, and I've found very little resources or interest – giving me the impression that either the solution is known and considered bad, or that is unknown but not worthy of research.
Is Hysteresis control undesirable? What makes it so?
Best Answer
Is variable-frequency a big deal? Imagine you are designing an EKG machine for testing patient's hearts. Those work by measuring tiny electrical pulses generated by the body. Now imagine the power supply had one filtering cap, designed to block 99.99% of 120Hz mains hum. A capacitor's ESR fundamentally varies with frequency, so while this cap may work very well to block 120Hz hum, it may do little to block 80kHz. So using a hysteretic supply, with it's widely-changing frequency, could switch at 80kHz, and result in a "ripple" of power which goes right past the filtering cap. The end result is a "blip" on the screen where there shouldn't be one. This is why voltage-mode PWM is used - the switching frequency is precise and known, so pulses at that frequency can be blocked.
Why does synchronization matter for a converter? For a single converter, there isn't anything to synchronize it to... unless controlled by any kind of clock-driven device, such as a CPU or microcontroller. But for multiple converters, synchronization is often necessary. Consider a modern PC motherboard's CPU and Voltage Regulation Module (VRM). The motherboard is supplied 3.3v at 40A, but the CPU needs 1.2v at 90A. So the VRM bucks 3.3v down to 1.2v. But no single device can switch 100A, so instead, three to six devices "take turns" bucking this down. Now if they all worked simultaneously, the output would be very noisy, as they all switch on and off at the exact same time. Instead, they are switched in sequence, or phase, which greatly reduces noise. To switch these in phase, requires them to be synchronized.
Why is high-ESR required for hysteretic control to work? My initial thought was, if there were zero ESR, then the output voltage would mirror the hysteresis of the comparator as a minimum. i.e., tons of ripple at who-knows-what frequency (dependent on capacitance value also.) Throw a power inductor in there, and this ripple could tend to oscillate or at least degrade stabilization. Perhaps I'll simulate it in LTSpice and see what that does.
Is hysteresis control undesirable? I wouldn't say so. Uncommon or minimalistic perhaps. PWM has been around for a long time and works reliably, but is more complex and expensive. Hysteretic is less expensivee, but frequency-variant. I think it's a great topic!
Here's an informative link about adding hysteresis to comparators.
EDIT: Here is the LTspice simulation results and .asc file contents. The LT1011 Comparator was used simply because it is a default component of the simulation package. Now there are many aspects of this design which are undesirable and prone to spurious behavior, so it is presented for informational purposes only. Click to open full-size.
This simulation result is highly dependent on the parasitic constituents of the circuit, and since no simulator includes all parasitics, I doubt it would physically work as robustly as shown. The MOSFET gates are capacitive, and the comparator is driving them directly - it is doubtful they would really switch as quickly and cleanly as simulated. It could even oscillate wildly - it has not been tested. But in this configuration, the output is remarkably stable for loads of 1mA, 100mA, 1, 2, 3A with good transient response. The output ripple (after filtering) is less than +/-5mV in all cases. The output filter does introduce a fairly nasty 3.5v spike when dumping the 3A load however.
If I were going to test this and use it for say, a microcontroller, I'd probably set
vref
to 3.8v or so and use a LDO regulator after it to ensure no spikes come through. Note that with some other comparators tested, overshoot at start-up was a real issue also, withvout
going as high as 4.5v for a few milliseconds.Sure, the start-up overshoot could be suppressed, and the output clamped with a crowbar circuit... but then for all this added complexity, why not just use a PWM drive instead? In any case, happy experimenting.