Your analysis will work when the output is forced to 1V instead of 0V. I was able to get the correct answer (output impedance is indeed lowered by loop gain!) by analyzing a 1V voltage source on the output.
The way that I prevent this sort of mistake is by being strict about how I write my equations. Among other rules, I don't introduce new terms like L and b, I don't use any numbers until the end, and I don't make approximations in the algebra. When the algebra becomes tedious, I use the Maxima computer algebra program. I think there is also a Mathematica package somewhere that does this type of analysis correctly.
In this problem, the rule that was violated is that the Vout term was replaced by a number before the equations were solved. In this case the number choice was unfortunate and it ruined the equation.
The more intuitive explanation is that Zout=Vout/Iout, so Vout=0 is a problematic choice.
I see your point but I think you worry too much about the changing Vgs (and thus changing Cgs).
The way this circuit works is that both NMOS and PMOS are considered to be working as source followers. For that to work properly the W/L of these MOSFETs must be large so that Vgs remains fairly constant over a varying Id.
These MOSFETs are Power MOSFETs so they will have a gigantic W/L, this is to ensure a low Rdson.
In practice I expect Vgs not to vary a lot so Cgs will also be fairly constant.
The main "error" introducing factor will be Vgs changing over Id so the more current you ask from the stage, the more distortion you can expect.
When designing a stage like this what I do is determine the input impedance (mainly a capacitance) of the MOSFETs. Since I'm an IC designer I do this in a simulator as there I will have models of my MOSFETs. You could also look in the datasheets and make a not of Cgs. Since the sources follow the gate voltage (more or less) there's almost no Miller effect to speak of so Cin = Cgs_pmos + Cgs_nmos will be a good approximation.
Now that I know the impedance I need to know the BW (bandwidth) I want because the output impedance (mainly resistance) of the driver stage together with the capacitive load of this stage will make an RC lowpass filter.
If I want a 1 MHz BW and the MOSFETS have a total capacitance of 4 nF then I would need the output resistance of the driver stage to be at least 40 ohms.
You already have 22 ohm gate series resistors and these are part of that 40 ohms so in your case I would need to drive IN with 18 ohms or less if I want that 1 MHz BW.
If you want to minimize / eliminate the errors introduced by Vgs changing over Id (load current) then I suggest that you add a feedback loop. Feedback the output voltage so that the gate voltage of the MOSFETs is such that the output voltage is as undistorted as possible.
The output impedance of the driver is related to the small signal behavior. This assumes that a certain current can simply be delivered and no clipping etc occurs.
You wonder about the actual current you would need to drive the output stage. Well, that depends on what large signal behavior you need. Slew-rate is something that comes to mind here. How fast do you want the output to be able to follow a large pulse-shaped input signal ? This will be limited by how fast you can change the gate voltages of the output stage MOSFETs. If you want rail-to-rail full swing in 1 us then you have to make sure that the driver stage can charge/discharge the gates within that 1 us.
Best Answer
In general source degeneration resistor "adds" a negative feedback to the circuit (current-series feedback). In this case, we sample the output current (\$I_D\$) and return a proportional voltage in series with the input (\$V_{GS} = V_G - I_D*R_S\$). This type of a feedback increases \$Rin\$ and \$Rout\$. But notice that the MOSFET itself has a very large \$Rin =\infty\$, therefore \$Rin = R1||R2\$ remains unchanged.
The voltage gain also drops to \$Av = -\frac{R_D}{R_S + 1/gm} = -\frac{R_D||R_L}{\frac{1}{gm} +R_S||R_3} \$
This also improves linearity, because without \$R_S\$ voltage gain is \$gm*R_D\$ and as you should know \$gm\$ varies with drain current. Because \$gm\$ is a function of drain current (\$I_D\$), the voltage gain will vary with signal swing and the voltage gain also. But if we add external source resistance \$R_S\$ we notice that the \$R_S\$ does not change with the signal swing (\$I_D\$ swing)so, the overall voltage gain is stabilized and is more linear.
For \$R_S >> 1/gm\rightarrow A_V\approx \frac{R_D}{R_S}\$
Now let us look at \$rout\$. If we are looking from the load perspective we can see two paths for a AC current to flow:
First through \$R_D\$ resistor.
And the second one through MOSFET channel -->\$R_S\$ into GND.
As you can see now \$R_S\$ resistor is in series with the MOSFET channel.
So, to find resistance seen from the drain terminal into the MOSFET we need to use a small-signal-model.
\$r_x = \frac{V_X}{I_X}\$ and because \$V_G = 0V\$ we have:
$$V_{GS} = -I_X*R_S $$
And from KVL we have
$$V_X = I_{ro}*ro+I_X*R_S$$
$$I_{ro} = I_X - gm*V_{GS}$$
$$V_X=\left ( I_X - \left (gm\left ( -I_X \right )R_S \right ) \right )ro + I_XR_S $$
And solve for \$I_X\$ $$I_X = \frac{V_X}{ R_S + ro + gm*R_S*ro} $$ And finally we have $$r_x = R_S + ro + gm*R_S*ro = ro(1+gmR_S+\frac{R_S}{ro}) $$
$$r_x = ro*(1+gmR_S)+R_S $$
As you can see adding \$R_S\$ resistor increase the MOSFET resistance.
The \$ro\$ is boosted by a factor of \$(1+gm R_S)\$
So, the overall \$r_{out}\$ is equal to:
$$r_{out} = R_D||r_x $$
and because \$R_D<<r_x\$ we have \$r_{out} \approx R_D\$