Is there a minimum clock rate specified by I2C? I know the most widely used clock rate is 100kHz and there is a "fast" mode of 400kHz supported by some devices, and a faster yet mode supported by other devices (I think 1MHz?). Since the SCK signal is generated by the master I presume one could operate at a much slower speed than any of those – is there a lower bound in practice? To what extent do slave devices care about the clock rate (e.g. is it common for them to have short timeouts)? The reason I'm asking is that I'm wondering if could possibly run I2C over a longer distance (e.g. 20 feet) to program I2C EEPROMs reliably in a production tester setup. I'm assuming it won't work reliably over that distance at the standard data rates. Am I off-base entirely in thinking that slowing down the clock speed will improve reliability over longer distances (e.g. is it really a question of drive strength and rise/fall times)?
Electronic – I2C minimum clock speed and reliability
clockeepromi2creliability
Related Solutions
Slew rate is how fast the signal changes from low to high, or vice versa. By limiting this abrupt transition, you can reduce ringing from signal reflections, and limit crosstalk between signal lines.
The way it works out, though, is that at 100kHz, the signal rates are so slow that the slew rate doesn't really matter; at 400kHz you may be able to fix an otherwise problematic circuit by limiting it; but then when you get to 1MHz you really need all the transition speed you can get, and so you just have to do good signal matching and route your lines more carefully.
The bit in question does nothing more than enable or disable the feature. The rest is simply advice. The speeds are in parentheses, as it is just a suggestion.
Except for the overhead it takes for the Start and Stop conditions, acknowledge bits, and device address plus R/W bit, they are the same.
So the more data that is sent per message, the closer the data rate will be to the clock speed. For very short messages (one address byte and one data byte), the data rate will be a little less than 50% of the clock rate. For very long messages, it will be more like 90%.
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Best Answer
No, there is no minimum frequency, minimum clock frequency is 0, or DC. See the specification, page 48.
But you will have to pay attention to rise and fall times. Those are 1000 ns and 300 ns maximum, resp. And a longer cable, with some capacitance will influence edges, regardless of frequency.
It's that capacitance, together with pull-up resistances that will determine rise time. Fall time is not a problem because the FET which pulls the line low has a very low resistance, and then the fall time time constant will be very low as well. So we're left with the rise time. To get a 1000 ns rise time on a 200 pF cable your pull-up resistors shouldn't be larger than 2.2 kΩ. (rise time to 90 % of end value.)
The graph shows maximum pull-up resistance (in Ω) versus cable capacitance (in pF) to get 1000 ns rising edges. Note that I2C devices don't have to sink more than 3 mA, therefore at 3.3 V the bus capacitance shouldn't be higher than about 395 pF, otherwise the pull-up resistance would have to be smaller than 1100 Ω, and allow more than the 3 mA. That's the greenish dashed lines. For 5 V operation the allowed capacity is even 260 pF, for a 1667 Ω pull-up value (the purple dashed lines).