IC with Pull-Down Resistors on SMBus Lines

wire capacitance is what you are fighting - you can only go as fast as you pullup resistors can charge the parasitic capacitance of the wires - in the real world you make a good guess and then once you start working with the circuits drop a 'scope on on the data line - if you see a bunch of nice square waves you're good to go. On the other hand if you see a bunch of shark fins some of which don't make it all the way high before the clock edge you're either going too fast or need a smaller pullup

Because I2C does not use a continuous clock, its always a little challenging to synchronize and capture a message, but it is do-able, and 100 Khz isn't an extreme rate. Now if you were developing a set of brand new I2C interface routines from scratch for a new library, you'd definitely want to slow down even further until the code was proven. If ou are using existing proven routines though, you may want to slow down anyway for now, because from the traces you've captured, I can tell you that these edges are terrible! I doubt any I2C receiver could decode a signal like that with any degree of reliability.

I'd like to hope, as others have suggested, that your scope sample rate is too low. But if each of those small "shelves" in the vertical lines are samples, then it looks like the signal slew rate itself is getting bogged down. In addition to slowing down the I2C clock, you may have to use stiffer pull up resistors, make sure to place them at every device along the chain, and sadly you may even have to re-examine your PCB traces. Are they long traces over a ground plane? Are there other sources of series resistance or shunt capacitance in these I2C lines?

Id take a look with a 100Mhz analog scope if you can, with X10 probes of course, if only to see if these edges are really as bad as they look, or just a trick of the scope. Do all you can to speed up these edges and figure out why they are so poorly defined. You really don't want to see any instances of non-flat peaks!