Background
I am designing a low power device where every uA counts. It has a temperature range from -25C – 35C.
In the datasheet for the 74AHC1G66; 74AHCT1G66, an analog switch I'm looking at, on page 4 it gives maximum supply current vs. temperature:
- 1 μA at 25°C
- 10 μA from -40°C – 85°C
Question
I can 'afford' 1 or 2 μA, but not 10. So, my question is: in a CMOS IC will supply current typically decrease with decreasing temperature? Even though the datasheet says at -40°C it could be up to 10 μA, will it most likely be under 1 μA?
I tried to research the answer to this. I found that for NMOS transistors iD is a function of temperature, from Wikipedia and Microelectronic Circuits Sedra and Smith. Contact potential increases with increasing temperature:
Vtn decreases with increasing contact potential:
iD increases as vT decreases:
Overall, this means iD increases with increasing temperature. Is this analysis on the right track? Or does it miss a lot of factors, for example, I think leakage is also a function of temperature.
Best Answer
The datasheet is providing a promise that 10 uA is the worst-case (non-switching) current across the -40 to +85 degC temperature range. As you mention, there are hints both in semiconductor physics and elsewhere in the datasheet that the high temperature condition is likely to be critical for power usage. Notice that as the temperature range extends upwards (the -40 to +125 degC column), the current balloons upwards by a factor of four.
The question, then, is how you use this knowledge. If you're building a one-off device, or a small number of prototypes, build-and-test is the way to go. I'd personally be surprised if you exceed a couple of uA under the given test conditions, so testing on an assembled board (if you can) is sane. If you're going to volume, you'll want to characterize the part (test a significant number, preferably from different batches; or characterize each batch as it arrives), or have the vendor (Nexperia) do it for you.
However, in terms of setting yourself up for success, there's other parameters you can tweak. Notice that the line under discussion in the datasheet specifies inputs at ground or Vcc (you'll likely be a few dozen millivolts off that, which works against you, but not much), and specifies Vcc = 5.5V, which is very much a worst case. It's extremely unlikely you're working with a 5.5 V Vcc, and if you're working on a low power device reducing Vcc is the most effective thing you can do to reduce power. It's not uncommon to see a quadratic reduction of current with Vcc -- so at ~2.5 V, you'd expect to see a maximum Icc of 2 uA or so across the whole -40 to 85 degC range.
This comes down to the common tension of interpreting datasheets -- are you worried about the worst case guaranteed by the vendor, the worst case you're likely to see in large volumes in the field (characterize rigorously, over conditions that are as close to the real ones as possible), or the worst case you'll probably see with a few prototypes (apply rules-of-thumb, adjust datasheet parameters conservatively, and get building)? For this application, at Vcc = 2.0 V - 2.5 V and -25 to +35 degC, I'd be extremely shocked if you broke 2 uA based on that datasheet; at Vcc = 3.3 V - 5.5 V I'd still be surprised, but in that case I'd do a test (or reduce Vcc).
One final note -- make sure that the Icc conditions stated reflect the case you care about. I already mentioned that they assume railed inputs, which is not true but true-enough for inputs near rails. But if you're switching this device at any significant frequency, the inputs are often right between the rails, not near them -- and the current usage in that case will (transiently) far exceed the given Icc. The current for this will usually be provided by a bypass capacitor near the device, but as frequency goes up the observed average current usage will go up, potentially well beyond 2 uA. Unless you're using this as a nearly-static device, measure!