Electronic – Identifier not declared in generic map, vhdl

vhdl

Following a previous suggestion in this post i tried to write by my self an example, but it doesn't work.

Top entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity topEntity is
    generic(m : natural);
    port(x : in std_logic_vector(m - 1 downto 0));
end topEntity;

architecture rtl of topEntity is
    component componentEntity is
        generic(n : natural);
        port(x : in std_logic_vector(n - 1 downto 0));
    end component;
begin
    INSTANCE : componentEntity
        generic map(n => m)
        port map(x(n - 1) => '0', x(n - 2 downto 0) => x(m - 2 downto 0));
end architecture rtl;

Component entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity componentEntity is
    generic(n : natural);
    port(x : in std_logic_vector(n - 1 downto 0));
end entity;

architecture foo of componentEntity is
begin
end architecture foo;

when i run ncvhdl -v93 it says:

ncvhdl: 15.10-s008: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
                port map(x(n - 1) => '0', x(n - 2 downto 0) => x(m - 2 downto 0));
                           |
ncvhdl_p: *E,IDENTU (topEntity.vhd,19|13): identifier (N) is not declared [10.3].

why it's not declared? it's a generic parameter properly initialized.

Update:

I putted:
port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));

The result is

ncvhdl: 15.10-s008: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
                port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
                          |
ncvhdl_p: *E,FMLNLS (topEntity.vhd,19|12): formal must be identified a locally static name 87[4.3.3.2] 93[4.3.2.2].
                port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
                                           |
ncvhdl_p: *E,FMLNLS (topEntity.vhd,19|29): formal must be identified a locally static name 87[4.3.3.2] 93[4.3.2.2].
                port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));
                                           |
ncvhdl_p: *E,UFPTID (topEntity.vhd,19|29): port (X) must be associated [1.1.1.2].

Updated 2…

Still trying to figure out what it is the problem with all these kind of declaration/mapping in vhdl… my new attempt is:

The error report that formal must be identified a locally static name

I found a glossary where each term of interest for this error is explained it also refers to the language standard:

 locally static name: A name in which every expression is locally static (if every discrete range that appears as part of the name denotes a locally static range or subtype and if no prefix within the name is either an object or value of an access type or a function call). (§6.1)

locally static expression: An expression that can be evaluated during the analysis of the design unit in which it appears. (§7.4, §7.4.1)

analysis: The syntactic and semantic analysis of source code in a VHDL design file and the insertion of intermediate form representations of design units into a design library. (§1 1.1, §11.2, §11.4)

There's also the error with the
port (X) must be associated

So i guess the problem could be that the name of the top entity input is x which is the same name as the component input. However i'm not sure about this because in general with port mapping like x => x don't cause any trouble to me…

Looking at the standard as static name it spits out that:

A name is said to be a static name if and only if one of the following conditions holds:
— The name is a simple name or selected name (including those that are expanded names) that does not
denote a function call, an object or value of an access type, or an object of a protected type and (in
the case of a selected name) whose prefix is a static name.
— The name is an indexed name whose prefix is a static name, and every expression that appears as part
of the name is a static expression.
— The name is a slice name whose prefix is a static name and whose discrete range is a static discrete
range.

Futhermore a specification is given for locally static name, which should help me to figure out the problem with the name:

a name is said to be a locally static name if and only if one of the following conditions hold:
— The name is a simple name or selected name (including those that are expanded names) that is not an
alias and that does not denote a function call, an object or value of an access type, or an object of a
protected type and (in the case of a selected name) whose prefix is a locally static name.
— The name is a simple name or selected name (including those that are expanded names) that is an
alias, and that the aliased name given in the corresponding alias declaration (see 4.3.3) is a locally
static name, and (in the case of a selected name) whose prefix is a locally static name.
— The name is an indexed name whose prefix is a locally static name, and every expression that appears
as part of the name is a locally static expression.
— The name is a slice name whose prefix is a locally static name and whose discrete range is a locally
static discrete range

So the issue should be that the name x doesn't fall in any of the categories listed, but why?

Best Answer

Try to replace your component instantiation with this:

INSTANCE : componentEntity
        generic map(n => m)
        port map(x(m - 1) => '0', x(m - 2 downto 0) => x(m - 2 downto 0));

Since n is not declared inside topEntity you can't use it. Your misconception is that the named generic n of componentEntity should be directly visible inside the port assignments region (that is port map (...)). This is not the case.
Since m and n are going to hold the same value (due to n => m) you can just use m when doing port assignments.

Related Solutions

Generic and generic map | total time delay for each files

Since the longest path in a half adder is only one gate, the delay of the entire circuit will be equal to the gate delay. In this case, the gate delay is 6 ns. The default values for gate_delay of both gate entities are overridden in the instantiations you write.

Note that your code will not work since and and xor are reserved words in VHDL. You will need to rename to something like and_gate and xor_gate

Another side note: VHDL code like this is only used for gate level simulation with timing annotations, usually after synthesis and place and route. If you want to write an adder in VHDL, you should write a <= b + c;

Electronic – illegal reference of a signal during a static elaboration, vhdl

It's helpful when asking VHDL to question to provide a minimal, complete, and verifiable example pointing to an error.

Here's a solution:

library ieee;
use ieee.std_logic_1164.all;

entity some_entity is
    generic (n: natural := 9);
    port (
        x:    in  std_logic_vector (n-1 downto 0)
    );  
end entity;

architecture foo of some_entity is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity some_entity_tb is
end entity;

architecture foo of some_entity_tb is
    constant n: natural := 9;
    signal signal_id:   std_logic_vector (n - 2 downto 0);
begin
INSTANTIATED:
    entity work.some_entity
        generic map (n)
        port map (
            x(n-2 downto 0) => signal_id,
            x(n-1) => '0'
        );
end architecture;

The entire bit analyzes and some_entity_tb elaborates and runs (without actually doing anything useful other than proving connectivity).

You have the ability in VHDL (incl. -93) to associate elements (members) of an array port formal separately.

IEEE Std 1076-1993 4.3.2.2 Association lists, para 14:

A formal may be either an explicitly declared interface object or member (see Section 3) of such an interface object. In the former case,such a formal is said to be associated in whole. In the latter cases,named association must be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object must be associated exactly once with an actual (or subelement thereof)in the same association list, and all such associations must appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object must identify the formal with a locally static name.

And to explain where the error message:

ncvhdl_p: *E,ILSGRD (test.vhd,159|32): illegal reference of a signal (SIGNAL_ID) during static elaboration [12.3].

came from:

IEEE Std 1076-1993, 12.3 Elaboration of a declarative part, para 3:

In certain cases, the elaboration of a declarative item involves the evaluation of expressions that appear within the declarative item. The value of any object denoted by a primary in such an expression must be defined at the time the primary is read (see 4.3.2 ). In addition, if a primary in such an expression is a function call, then the value of any object denoted by or appearing as a part of an actual designator in the function call must be defined at the time the expression is evaluated.

It's telling you that you can't assign an expression as an actual to a formal unless the value of the object signal_id is known at elaboration time, and a signal's value isn't known until after elaboration:

NOTE--It is a consequence of this rule that the name of a signal declared within a block cannot be referenced in expressions appearing in declarative items within that block, an inner block, or process statement; nor can it be passed as a parameter to a function called during the elaboration of the block. These restrictions exist because the value of a signal is not defined until after the design hierarchy is elaborated. However, a signal parameter name maybe used within expressions in declarative items within a subprogram declarative part, provided that the subprogram is only called after simulation begins,because the value of every signal will be defined by that time.

Best Answer

Related Solutions

Generic and generic map | total time delay for each files

Electronic – illegal reference of a signal during a static elaboration, vhdl

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