Electronic – Impact of the channel length on the threshold voltage in CMOS transistor

M2 is essentially acting like a pullup resistor in this case. Real resistors are difficult to make on silicon chips, so a PFET in on-state is good enough for this purpose.

The chip designer can vary parameters like the channel length, width, and possibly doping level. Depending on the characteristics of the transistor, it could act more like a current source than a resistor at the operating point. Sometimes a "long tail FET" is used to make a rough current source. Without knowing the parameters of M2, we don't know if it is more like a resistor or more like a current source, although in this application that wouldn't make much of a difference. Ideally you'd want a current source for a pullup, but lots and lots of places you see resistors doing that job well enough.

When you apply a voltage to the gate of an NMOS FET that is greater than the threshold voltage \$V_{t}\$, a channel of electrons is formed under the gate. That channel connects the drain and source so that when you apply a voltage \$ V_{ds}\$, a current flows from between these terminals. In this mode, the MOSFET behaves almost like a resistor, so the current flow depends (although not linearly) on \$V_{ds}\$, but the current will also increase with the gate-source voltage \$V_{gs}\$ because increasing this makes the channel deeper, reducing its resistance. That explains the first part of the curve (active or triode).

However, the electric field near the drain depends not just on \$V_{gs}\$ but also on \$V_{ds}\$. Once \$V_{ds} = V_{gs} - V_{t}\$ (called \$V_{ds,sat}\$) the electric field is cancelled near drain and the channel becomes shorter, no longer reaching the drain, leaving a depletion region between the end of the channel and the drain. Any further increase in \$V_{ds}\$ is dropped across this depletion region so the voltage across the channel stays constant at \$V_{ds,sat}\$ and the current flow is also constant. That is the second region of the curve (saturation).

The explanation of the saturation region above would suggest that FET current is constant with \$V_{ds}\$ in the saturation region. Obviously, from the current-voltage curves we can see that this is not the case, and actually the current slowly rises. This is due to an effect called channel length modulation. As \$V_{ds}\$ continues to increase, it cancels the inverted channel even further from the drain, leading to the channel shortening. This reduces the channel resistance (resistance is proportional to length) leading to higher current flow.

There are obviously a lot of second order effects not covered here, but those are the basics!