Electronic – In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth

counterdigital-logicflipflopripple-counter

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and not the first and fourth since it's the first and fourth bits that are 1s.

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Best Answer

The circuit you cited is a ripple counter, not a synchronous counter. It actually has eleven states, 0000 through 1010, but as soon as the last state is reached, the NAND gate immediately (asychronously) resets the flip-flops to the 0000 state.

In a synchronous counter, all of the flip-flops would share a common clock, and you'd control the sequence of states by driving their J and K inputs. This would require a few additional gates, which would include decoding the 1001 state so that the counter goes directly to the 0000 state on the next clock edge.