In an NMOS, does current flow from source to drain or vice-versa

Note that this is not a power converter but effectively a chip that uses a PFET to implement active rectification. As such, the current is intended to flow from the battery to the load when the switch is on. The FET is being used like a diode, making use of the inherent body diode of the part. The chip then turns on the FET to make the diode look more ideal when it should already be on. The chip will turn off the FET quickly when is sees SENSE go higher than Vin. If it didn't, the "diode" would conduct backwards.

The advantage of such a design is that the effective diode has very low forward drop, which is useful when it's in series with a battery since less of the battery power will be wasted. The drawback is that the overall diode has slow reverse recovery time, since the chip has to sense the reverse voltage and then actively shut off the FET. In this case the diode is used for power ORing, so a few µs reverse on time won't matter much.

The voltage that must be greater than \$V_{TN}\$ is the voltage from the gate to the source, \$V_{GS}\$, not just the voltage at the gate. Once the source voltage rises to \$V_{DD} -V_{TN}\$ the voltage from the gate to the source will just equal \$V_{TN}\$. Any increase in the source voltage will cause \$V_{GS}\$ to be less than \$V_{TN}\$ so current flow will stop. Therefore, the voltage at the transistor's source can't rise above \$V_{DD}-V_{TN}\$ (based on this simple model).