Electronic – In which cases should I use Z as output in HDL

fpgahdlvhdl

I created a simple multiplexer which feeds different input into output depending on statemachine.
Now there are states when I do not need the output so I usually set it to 0.

INST <= "01" WHEN fsm_state =  read_first_half
                OR fsm_state =  read_second_half 
                OR fsm_state =  next_r ELSE
      "10" WHEN fsm_state =  write_first_half   
                OR  fsm_state =  write_second_half 
                OR  fsm_state =  next_w 
                ELSE  "00";

As far as I remember there was a third syntetisable value 'Z'. I far as I remember it's floating value with high impedance.
When do I use it and is it safe to use? Will it be syntetisable on all FPGAs?

Best Answer

When you don't care about an output value given a set of inputs, use '-' which means "don't care". The synthesizer will simply assign values that optimize resources/performance. Note that a simulator however has the option of keeping '-' as an actual value, and this will actually help you in making sure that having a "don't care" in there will not impact the relevant parts of your design.

'Z' or "high impedance" in FPGAs is only used for tri-state outputs, which nowadays are only available at the actual pins of the chip, not for internal logic. Modern FPGAs manufacturers simply don't allocate internal routing resources for them, and are only intended for interfacing with external chips/components. For internal logic the same functionality (such as bus arbitration) can be achieved with regular logic gates instead.

These definitions can be found in the IEEE std_logic_1164.vhdl library: http://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164.vhdl

Related Solutions

Electronic – Do I need to reset the FPGA design after startup

You should assume the clock input to your flip-flops is toggling unless you can prove otherwise (by a guaranteed power on or post configuration delay). All the flip-flops on a given clock domain are not guaranteed to start on the same clock edge based on GWE or GSR. Both act like an asynchronous reset and cause potential problems for some logic (counters, one-hot state machines, etc).

Specifically a one-hot state-machine that transitions immediately after configuration WILL (eventually) FAIL (transition to an invalid state). The frequency of failure will depending on the clock period compared to the device (and place and route) specific skew for your design.

Another simple experiment to see this behavior initialize a relatively fast count down counter with 10000000 and look at its behavior immediately after configuration. Some bits make the transition to 01111111 and some bits miss that first transition but the subsequent counting sequence will be correct.

The white paper mentioned by Krunal Desai talks about this very problem and is a great reference. Any SRAM based FPGA will most likely have a similar issue.

There is no need to reset the registers to get a known value. If you have logic that is sensitive to all starting on the same clock edge will need to add synchronization logic (this can consist of a synchronously de-asserted reset or other synchronous logic). Xilinx AR44174 talks about the issue a little more. I would add a third method of mitigation which is to guarantee clocked logic is not changing/transitioning during the first several clock cycles after startup.

Electronic – Using string type in VHDL

I think you really want an enumerated type. They will show up named in the simulation without the hassle of strings. You will need to check them out to figure out completely how to use them. Here are the basics:

-- declaration   
type my_enumerated_type is ( good, bad, ugly);
signal rating, rating2 : my_enumerated_type;
constant ENCODED_TYPE_WIDTH : natural := 2;

-- helpers - use a function like this to convert between enumerated type and std_logic_vector
function encode ( rating : my_enumerated_type ) return std_logic_vector is
begin
  return std_logic_vector(to_unsigned(my_enumerated_type'pos(rating), ENCODED_TYPE_WIDTH));
end encode;

function decode ( rating : std_logic_vector ) return my_enumerated_type is
begin
  if unsigned(rating) < my_enumerated_type'length then
    return my_enumerated_type'val(to_integer(unsigned(rating)));
  else
    return ugly;
    -- TODO: throw an error instead? like so: 
    -- assert false report "rating out of bounds in conversion to my_enumerated_type" severity ERROR;
  end if;
end decode;

-- conversion
output  <= encode(rating);
rating2 <= decode(input);

These enums can be fun and powerful in VHDL. Enjoy!

Best Answer

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Electronic – Do I need to reset the FPGA design after startup

Electronic – Using string type in VHDL

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