Electronic – “Input high voltage common mode range?”

In the circuit you showed one would generally make the pole for the differential signal smaller (~20 times) than the common mode pole. The reason for this is due to component tolerances. If the common mode filter for the one leg has a different pole frequency then this would affect the differential signal. This is because the filtering is no longer identical on both sides.

This could cause worse interference than not filtering, since the differential OP-AMP and ADC should have at least 50dB CMMR at low frequencies (if not higher).

If the differential pole is lower, then when the common mode filters start "interfering" there is no longer a differential signal of interest. This will prevent high frequency CM noise interfering with your measurements. This is important as CMMR drops off with frequency.

The ADS1675 is a high speed ADC which runs of a \$5\mathrm{V}\$ Single-Ended power supply. If you note the following tables from the datasheet:

The differential input must be referenced to mid point of the supply rails which in this case requires a common mode voltage of \$2.5\mathrm{V}\$.

You then have an input full scale range of \$\pm3\mathrm{V}\$. I can only presume there is some attenuation internally which means that this full scale range is brought to within the specs of the device (need to clear that up with some more reading).

The circuit you show is for a THS4503 which is a high speed fully differential amplifier. The purpose of this is to either buffer or amplify the incoming signal to the full scale range of the ADC, and critically to drive the sample/hold capacitance of the ADC input.

Because of the high speed, you need a pretty strong driver to ensure that the capacitance of the sample capacitor in the ADC is driven quickly to the level of the incoming signal. This requires a fairly high current to drive the capacitor at high frequencies. So if you have a weak signal source it is important to amplify it before driving the ADC.