I am trying to build a measurement circuit that is capable of measuring voltage signals in the order of micro volts.
Signal Characteristics:
Voltage: Anywhere between 1 uV to 100 uV
Frequency: Minimum 10 kHz to maximum of 50 kHz.
The signal needs to be converted to the frequency domain. It is very important for me to measure the odd harmonics. I am planning to do this on a PC after ADC processing.
Current Design:
Currently I am using a 24 bit ADC ADS127L01 from Texas Instruments. I have followed all the design recommendations. I am using a reference voltage of 2.5 V and as per the datasheet will be using an ADC driver THS4551 as well.
Question:
Do I need to use an instrumentation amplifier for this design? I do not think it will be very helpful as I am using a 24 bit ADC, but I am worried about losing bit resolution due to noise and layout issues.
Best Answer
Here is a 3-stage 90 dB (30,000:1) non-instrumentation-amplifier circuit, using the OPA211 with its 1 nanoVolt/rtHz noise floor; in 100KHz bandwidth that becomes 316x (sqrt(100,000)) larger at 0.3 microVolts Referred To Input (RTI). Input signal is 100 microVolts PeakPeak. The FOI Frequency Of Interest (see top rightcorner), used for SNR and ENOB, is set to 50,000Hz. Prior to the ADC (24 bits, 200,000 Hertz Fsample) I included a RC low pass filter of 200KHz bandwidth, to ensure the harmonics are included.
Result (with all the Gargoyles ---- the Interferers ---- turned off) is 5.7 bits --- broadband random noise. If you narrow the bandwidth by 10 octaves, or to 200Hz FFT bins, your floor should be improved by 30dB, or 5 more bits, to about 0.1% RMS error.
If you want, I'll add some specific HFI such as black-bricks, or EFI such as nearby MCU clocks, or PowerSupply trash, or Ground upsets.
===== result of adding 3 electric field interferers and 1 Ground interferer =======
YOU ARE IN LUCK. Despite only 1milliMeter spacing from electric field (EFI) interference with MCU clock, 60Hz power wire, and 60Hz power with SPIKES, to the various Signal Chain nodes, the FILTERED OUTPUT into ADC still provides 5.7bits. Advice: keep the MCU clock and MCU output traces at least 1mm away from the Signal Chain. Ditto for power wiring (and any unfiltered external VDD traces).
Why does EFI not degrade the Signal Chain? Because ALL the nodes are LOW impedance, and the displacements currents induced by changed electric fields are below 1 millivolt. Notice the Random Thermal Noise remains the dominant Code Spread cause.
If the RC LPF is "deselected", then the total Aggressors increased from 354 microVolts, to 14,000 microVolts, and the ENOB drops from 5.7 to 4.9 bits.
========================= design details ===================
Sensor: 0.5 ohms and 1uH
Stage#1: 1nanoVolt/rtHz noise density; Rg (to ground) 26 ohms; Rfb 497 ohms
Stage#2: 1nanoVolt noise density: Rg 19 ohms; Rfb 282 ohms
Stage#3: 1nanoVolt noise density: Rg 95 ohms; Rfb 9,400 ohms
Stage#4: 200KHz RC LPF R = 1,590 ohms; C = 500pF
Stage#5: ADC 5volts PP; 24bits, 200,000Hz Fsample, Rin = 50 ohm, Cin = 48pF
=========== Are ALL the nodes Low_Z, so EFI is mostly ignored? ========
Yes. Here is Zout of Stage#1
Notice the EFI energy (capacitively coupled into ALL the nodes) arrives at a rather LOW output impedance for OpAmp #1, because the OpAmp has 45MHz Unity Gain BandWidth and has strong control of the OpAmp output voltage up to 1MHz.