Electronic – Interface Mobile SDRAM (1.8V) with 3.3V SDRAM controller

In theory it is possible. In practice, it sounds better than it really is.

It only really works when the chips are not BGAs. But these days almost all modern CPU's and SDRAMs are in BGA packages. Putting BGA's on opposite sides of the PCB can be problematic because you quickly run out of room for pads and vias. But the benefits of using BGAs (reduced pin inductance, etc.) is very nice for meeting EMI regulations and I tend to choose BGAs over other packages.

So the only time that you can really put the CPU and SDRAM on opposite sides of the PCB is when your CPU and SDRAM are old-ish. Switching to BGAs and modern parts can often save you PCB space over those parts anyway, so you are not really gaining anything by sticking with the old technology and non-BGAs.

Disclaimer: I do know of some exceptions to what I claim above. Sometimes BGAs are just not an option.

Sharing the same address/data busses for several physical memories is not difficult, as is routing the signals. But you do have to pay attention to how your traces are laid out and terminated. You might also have to add layers to the PCB to make room for routing.

Unless your microcontroller has a direct bus support for interfacing to DDR/DDR2/DDR3 type RAM or your microcontroller is interfaced through an FPGA which has been programmmed to provide the RAM interface then it is likely that futzing around with DIMMs is not a useful exercise. There are several strong reasons why this is the case....

1) DDR memory chips may be operating at lower voltages than your microcontroller.

2) The interface to the DDR memory is multiplexed and requires precise clocking whilst the multiplexed lines change states in sync with said clock.

3) Modern DIMMs are designed to operate at very high frequency clocks of 800MHz, 1066MHz, 1333MHz, or 1600MHz. Signal integrity is extremely extremely important when designing the circuit connections to the DIMM. It is not a trivial exercise and the memory chips can be extremely sensitive to noise as a result.

4) DDR memories require constant refresh to keep the memory cells data valid. Without refresh the memory content fades away over time from milliseconds to seconds.

5) The command structure to operate modern DDR RAMs is complex. The most complicated part is getting the initialization sequence correct which consists of some 13 to 20 individual steps.

6) Modern DIMMs are designed to feed data to modern PC type computers very fast. The typical DIMM has a data path width of 64-bits. Multi rank DIMMs also require multiple clocks and chip select signals to access all of the memory chips on the memory stick. It is unlikely that the typical small microcontroller can make effective use of this wide data format without an excessive amount of external circuitry.

Keep this in mind too. Companies that make PC style processors that utilize DIMMs have onboard controllers to interface to the memory sockets. There is an engineering specialty for programmers that work in the BIOS field called MRC (memory reference code). This is the program code module that initializes the DDR controller and all the attached DIMMs. This specialty employs the best and some of the most senior BIOS programmers that do nothing but MRC coding as a full time job.