Electronic – interfacing multiple ADC: sharing master clock


My project involves interfacing two analog-digital converters to an STM32F411RE microcontroller.
The first ADC is an ADS1191, the second is an ADS1158.

Those two ADCs will have to convert signals simultaneously and their samples retreived by the MCU.

I've been used to work with a single ADC. The program is interrupted as the DRDY (data ready) pin goes low, and the samples are retrieved.

The questions are:

Do I need to make sure the two ADCs share the same master clock? If yes, I suppose I should use the internal clock of one of them, and feed it to the external clock pin of the second one.
ADS1191 has an internal clock of 2MHz and requires an external clock of 2MHz.
ADS1158 has an internal clock of 16MHz and requires an external clock of 0.1 to 16mHz. Is it safe to use ADS1191 internal clock and feed it to ADS1158? Will I have to sacrifice anything by feeding a master clock of lower frequency (2MHz vs 16MHz)?




The "continuous read" mode which I'm used to use with a single ADC consists in connecting an interrupt signal to the DRDY (data ready) pin of the ADC. When data are being sampled, the DRDY pin switches high. Then, when the data are ready to be transferred, the pin switches low. The MCU detects the falling edge of DRDY and starts transferring the data byte-per-byte.

What I'm looking for is to have "correlated" samples, i.e. make sure that two respective samples from each ADC retrieved at the same time indeed correspond to the same time "bin", which might not happen if the respective master clocks show a drift.
From the valuable answers below, I conclude the following regarding the use of two (or more) ADCs.

Suggested solution
Make sure the two ADCs share the same master clock. In my application I'm able to redirect the internal master clock of the first ADC to an output pin. This clock signal would then be fed to as "external clock" on the second ADC. To reduce the frequency (which most of the time is related to the sampling rate), one can resort to a d-type flip-flop (to divide freq. by two).
The principle would therefore be the same as in a single ADC application: trigger interrupt on DRDY of one ADC (the one with shortest hold time). When this first transfer has finished, retrieve samples from the other ADC.

Best Answer

If you wish to have the same number of samples per second, then you will need to peruse the datasheets very closely. What you specifically mean by 'simultaneously' needs clarification. All I can show you here is how to achieve correlated samples at the same rate.

The ADS1158 shows (datasheet figure 128) shows a fixed channel mode at its simplest with the data rate at Fclk/128. This appears to be the sample rate.

The ADS1191 is optimised for sample rates of <=8kS/s. Using the 8kS/s rate would therefore be the best you can achieve, according to the manufacturer.

There is an option for an external clock on both, so lets see what you can do.

The ADS1191 accepts a 2.048MHz clock (see the datasheet for details of pin connections as the modulator is expected to run at 128kHz).

To get the 8kS/s rate from the ADS1158 in the simple mode above, yields a master clock of 1.024Mhz. Note that there are limited options to change the sample rate in this part

This is fortunate: Generate a master 2.048MHz clock for the ADS1191 and divide it by 2 to yield the external clock on the ADS1158.

If you now start each conversion at the same instant, you will get conversions that take the same amount of time, and the sample rate is correlated.

Note that the 2.048MHz clock for the ADS1191 was only implemented to enable faster SPI access - you should not attempt to run the modulator above 128kHz.

[Update in response to comment]

I suggested a master clock because that was one method of achieving the desired result; as you note, there are other methods.

A D type flip flop with #Q to D is indeed a standard way to divide a clock by 2.