I while ago I asked this question about interfacing static ram to an fpga for the purposes of a vga frame buffer I wanted to make as a little hobby project. It became clear to me at the time that the project was too difficult for my level of knowledge (as I'm basically a c++ programmer and knew little about electronics) but since then I've built a few smaller cpld based projects so now feel I know enough to look at the project I want to build again 🙂
I'm thinking of using this memory chip as it seems to fit my requirements. The data sheet indicates that I can read a data byte every 10ns and that I have to set up the address a minimum 10ns before I want to read the data. It has a "Data Hold from Address Change" time of 3ns.
This implies to me that assuming a 10ns clock I can simply set the address lines each clock cycle, and read back the data from the previous address. That the data output will be valid at or before the next 10ns clock, and will remain valid for at least 3ns after I change the address , so it's safe to read it.
Is this a reasonable thing to so (setting the address at the same time as I read back the data from the previous address). From looking at the data sheet it seems so.
This is the fastest it would work, I could also use a slower clock if pushing the timing to the limit like this was a problem, I just wanted to understand if I'd understood the data sheet correctly.
Best Answer
I assume you're looking at "Read Cycle No. 1". Yes, that's the correct interpretation of the datasheet.
Now you have to worry about the FPGA side, which has its own setup/hold times and delays. If you have enough frequency headroom on the FPGA you don't need to worry much about this beyond basic timing constraints; the tools will abstract things away to some extent. But eventually you will find something that needs to be micromanaged, so it helps to start thinking about these issues now. I suggest completing the HDL side of your project (read those timing reports) before finalizing your hardware design.
Operating an external 100 MHz interface on budget FPGA families is probably going to require some care. You can start low and slow, though, like a few tens of MHz, before really getting your feet wet.