Electronic – IR2110 Simulation not working in LTSPICE

ltspice

I am trying to implement a half bridge topology as shown in the figure below:

I have replaced the IRF450 with STGW40H60DLFB IGBT.

I have also replaced the 11DF4 with UF4007.

My LTSPICE schematic looks like:

My VDS and VGS in the high side and low side is:

When I run my LTSPICE simulation with a pulse with 100K frequency, I get:

I can't spot a error in my LTSPICE, please let me know if you have any idea what it might be.

MODEL Used for UF4007:

.MODEL UF4007 D N=3.97671 IS=3.28772u RS=0.149734 EG=1.11 XTI=3 CJO=2.92655E-011 VJ=0.851862 M=0.334552 FC=0.5 TT=1.84973E-007 BV=1000 IBV=0.2 Iave=1 Vpk=1000 type=silicon

Spice Model for IR2100 was downloaded from:
https://www.infineon.com/cms/en/product/power/gate-driver-ics/ir2110/

Spice Model for STGW40H60DLFB was downloaded from:
https://www.digikey.be/product-detail/en/stmicroelectronics/STGW40H60DLFB/497-14364-ND/4696260

Best Answer

It looks like you used an autogenerated symbol for your IGBT, but you connected it wrong, because the order of the pins is D-G-S. But, instead of using an autogenerated symbol you can make things easier for you if you choose the [Misc]/nigbt symbol, which you can use directly as an IGBT. All you have to do is rename NIGBT with STGW40H60DLFB-V2, and you're done.

You still have to add the correct prefix (right-click on the symbol, change Z to X), I thought that would be implied.

Anyway, the IGBT subcircuit is full of behavioural expressions and it's not very convergence-friendly. I don't know if it will help with your particular schematic, but I poked around and managed to get it working in a simple test by making these changes inside the STGW40H60DLFB-V2.lib file:

on line 70 change r_escusione 1z a1 500 to c_escusione 1z a1 10p Rpar=500
on line 73 change r_conv1 1y a1 10 to c_conv1 1y a1 10p Rpar=10
on line 114 there's a Grg1 ...; add this line, crg1 g2 g 10p rpar=1g right below it
on line 168 add a ; at the beginning of the line, in front of E2 ..., then add these two lines below:

g2 50 40 g d1k 1k
r2 50 40 1m

on line 204 add a ; at the beginning of the line, in front of E22 ..., and add these two lines below:

G22 502 402 ss d1k 1k
r22 502 402 1m

You can help in your schematic by setting Rser=10...100m for the voltage sources (V3, V4, and V1; V2 can be ignored), adding Rser=1...10m to capacitors (all four), and adding Rpar=10...100k to the inductor. Also try changing V2, A1 and their connections like this:

delete A1 and all the connections to the input pins HIN and LIN. V2 should be just sitting there in the schematic with no connections.
add [Digital]/buf (not buf1) and connect its input to V2 and its outputs to HIN and LIN pins. There should be a new A1 in the schematic.
add vhigh=6 tau=10n tripdt=30n to the new A1.

These changes could help, too:

add Vp=0.3 to the .model UF4007 card
add this model for the 1N4148:

.model 1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 Vp=0.3 mfg=OnSemi type=silicon)

Try running your schematic with these changes. If you're religious, praying might help.

Related Solutions

Electronic – IR2110 LTspice simulation weird behaviour

On startup, your bootstrap capacitor C3, C4 need be charged through D2 to VS then R1 to ground. If your R1 is too large, the charging time will be long. Assume R1 = 1k ohms, and C3 = 22uF, then

$$ \tau = C3 \times R1 \approx 22ms $$

This causes about 50ms 10% ~ 90% rising time. Because the high side driver supply actually floats on your load, so as the capacitor voltage rising, the lower slope line reflect the voltage change on your load resistance.

When you change the load resistor to 10 ohms, the time reduced to about 500us.

Electronic – LTSpice D flip-flop not working

If you go to the LTspice help and navigate to "Special Functions" you'll see a list of parameters that can be selected for the digital components, including the Dflop.

Your shift register didn't work because it had no output rise or fall time associated with it, so everything was happening all at once!

Also, the digital stuff defaults to a Vcc of 1 volt.

I've redrawn your schematic so everything starts cleared, Vcc is 5 volts, and put some delay into the Dflops, and now it works. :)

If you right-click on any of the dflops, that'll bring up the attribute editor, which will show their edited (non-default) parameters, specifically:

SpiceLine = Vhigh 5 Trise 10n

and will allow you to modify any of the component's editable attributes.

Here's the schematic and the plot, which I edited to look like a timing diagram:

and here's the circuit list:

Version 4
SHEET 1 1732 752
WIRE 48 -144 -256 -144
WIRE 352 -144 48 -144
WIRE 656 -144 352 -144
WIRE 864 -144 656 -144
WIRE 1104 -144 864 -144
WIRE 1360 -144 1104 -144
WIRE 1616 -144 1360 -144
WIRE -128 -64 -368 -64
WIRE 176 -64 -64 -64
WIRE 480 -64 240 -64
WIRE 784 -64 544 -64
WIRE 864 -64 864 -144
WIRE -256 0 -256 -144
WIRE 48 0 48 -144
WIRE 352 0 352 -144
WIRE 656 0 656 -144
WIRE 1104 0 1104 -144
WIRE 1360 0 1360 -144
WIRE 1616 0 1616 -144
WIRE -368 48 -368 -64
WIRE -336 48 -368 48
WIRE -160 48 -176 48
WIRE -64 48 -64 -64
WIRE -32 48 -64 48
WIRE 144 48 128 48
WIRE 240 48 240 -64
WIRE 272 48 240 48
WIRE 448 48 432 48
WIRE 544 48 544 -64
WIRE 576 48 544 48
WIRE 1024 48 736 48
WIRE 1280 48 1184 48
WIRE 1536 48 1440 48
WIRE 1728 48 1696 48
WIRE -336 96 -368 96
WIRE -128 96 -128 -64
WIRE -128 96 -160 96
WIRE -32 96 -128 96
WIRE 176 96 176 -64
WIRE 176 96 144 96
WIRE 272 96 176 96
WIRE 480 96 480 -64
WIRE 480 96 448 96
WIRE 576 96 480 96
WIRE 784 96 784 -64
WIRE 784 96 752 96
WIRE 1024 96 992 96
WIRE 1280 96 1248 96
WIRE 1536 96 1504 96
WIRE -368 208 -368 96
WIRE 992 208 992 96
WIRE 992 208 -368 208
WIRE 1248 208 1248 96
WIRE 1248 208 992 208
WIRE 1504 208 1504 96
WIRE 1504 208 1248 208
WIRE -256 288 -256 144
WIRE 48 288 48 144
WIRE 48 288 -256 288
WIRE 352 288 352 144
WIRE 352 288 48 288
WIRE 656 288 656 144
WIRE 656 288 352 288
WIRE 1104 288 1104 144
WIRE 1104 288 656 288
WIRE 1360 288 1360 144
WIRE 1360 288 1104 288
WIRE 1616 288 1616 144
WIRE 1616 288 1360 288
WIRE -368 336 -368 208
WIRE -256 336 -256 288
WIRE -368 448 -368 416
WIRE -256 448 -256 416
WIRE -256 448 -368 448
WIRE -368 512 -368 448
FLAG -368 512 0
FLAG 864 -64 0
SYMBOL voltage -368 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1u 5n 5n 0.5u 1u)
SYMBOL voltage -256 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 50n 50n 100n)
SYMBOL Digital\\dflop -256 0 R0
SYMATTR InstName A1
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 48 0 R0
SYMATTR InstName A2
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 352 0 R0
SYMATTR InstName A3
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 656 0 R0
SYMATTR InstName A4
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1104 0 R0
SYMATTR InstName A5
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1360 0 R0
SYMATTR InstName A6
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1616 0 R0
SYMATTR InstName A7
SYMATTR SpiceLine Vhigh 5 Trise 10n
TEXT -352 480 Left 2 !.tran 0 30us 0

Best Answer

Related Solutions

Electronic – IR2110 LTspice simulation weird behaviour

Electronic – LTSpice D flip-flop not working

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