I have read that initial values to a signal can be set in an FPGA since the design is "loaded into it" after power up. However, in ASICs we can only rely on a reset signal to put all signals into a known state. Thus, is assigning initial value to all signals in code that shall be synthesized a good practice?
I have also read that reset signals makes heavy use of routing resources in FPGA and also in ASIC requires to be routed everywhere. In FPGAs, not using reset in every single register is a way to reduce use of routing resources but am not sure what benefit it is in ASICs. Is it a good practice to find ways to reduce use of reset signal in synchronous design by not using it in some parts of design but use it in others?
Best Answer
I would say that there are a couple of different ways that you could argue that. Not sure what the 'best' method is in general, it's going to be dependent on what you're trying to accomplish. It's easy to initialize everything on the FPGA in HDL so that when it comes out of the configuration routine, everything starts from a known state. However, usually resets are necessary, even on an FPGA, due to various clocking configurations. In which case, NOT initializing things may make more sense as then X propagation can be checked in simulation to make sure the resets are doing their job properly by resetting the appropriate registers.
In terms of routing, it makes sense to figure out what ACTUALLY needs to be reset and then omitting resets on things where the initial configuration doesn't matter. This will save routing resources on both FPGAs and ASICs. For example, things like data buses with valid signals don't need ANY of the data bus to be reset, only the valid signals. If your data bus is 32 or 64 bits wide, only resetting the valid signals will significantly reduce the complexity of the reset circuitry. The reduced routing complexity can lead to smaller resource utilization and easier timing closure. It also allows the synthesizer to use the reset inputs of the flip flops for other purposes, which could simplify the logic and again improve area and timing.
Also, what you reset and how you do it (sync vs. async, reset to 0 vs reset to non-zero) may affect how the synthesizer can infer things like RAMs. Pipeline registers in block RAM don't necessarily have reset or preload capabilities, so if your reset logic conflicts with what the block RAM on your target chip is capable of, then your pipeline registers won't get merged and your timing performance and resource utilization will suffer.