Electronic – Is it ok to ‘snake’ the flow of the schematic

One little nit: Only really sloppy developers use daily builds because one build a day means having to wait up to a day to find out if you broke the build.

The best solution is to build and test every single change individually before letting it hit the public branch and revert the change if it breaks the build in any way.

Doing any sort of automatic testing on a schematic or a board layout might be very hard or impossible, but everything you can automate should be automated via something like Hudson, things that come to mind are:

• ERC
• DRC
• BOM updating (check that the parts exist, are available and calculate total cost)
• Generate Gerbers and other manufacuring files.
• Generate PDFs of the schematic and PCB layers as well as 3d renderings of the PDB, BOM diff and other documentation.
• Drop a mail to the developer mailing list with the commit message and links to the output files, so developers can review the change easily.

The number of errors that can be caught automatically might not be terribly high, but having the CI system generate the output files means that it will happen correctly every time and that you don't forget some silly setting when doing it manually.

You are right, in that a common ground is needed between the circuits connected to each port of the translator.

However, this particular circuit fragment depicted in your diagram of the translator out of context does not involve any connections of its own to ground apart from the possible ones through whatever is connected to its ports.

Effectively, this circuit is a sort of bidirectional pass gate, sitting between two pullup resistors which can generate high states. Generating low states is left to the drivers connected to it, which would presumably have some kind of low-side switch that can connect to their shared ground. If either side does that, the other will see the "low" pass through the FET, while if neither does so each sides see a pullup towards its own positive rail.

It would be useful if that schematic diagram had a nice clear net line between the ground ports on each side. It may have been prepared in a style where the name of the ground terminals being common means that they are in fact connected in the netlist (as they would need to be on the PCB), despite this not being shown visually.

Here's an excerpt from the xml-format Eagle schematic:

<net name="GND" class="0">
<segment>
<wire x1="25.4" y1="88.9" x2="27.94" y2="88.9" width="0.1524" layer="91" style="longdash"/>
<pinref part="JP1" gate="G$1" pin="3"/>
<label x="27.94" y="88.9" size="1.27" layer="95" xref="yes"/>
</segment>
<segment>
<wire x1="66.04" y1="88.9" x2="63.5" y2="88.9" width="0.1524"     layer="91" style="longdash"/>
<pinref part="JP2" gate="G$1" pin="4"/>
<label x="63.5" y="88.9" size="1.27" layer="95" rot="R180" xref="yes"/>
</segment>
</net>

Which indicates there there is a named "GND" net having two visually separate segments, which are nonetheless the same net as they have the same name.