Electronic – Is operating point calculation the same for P-JFET and N-JFET with voltage-divider bias

I would like to know if it is possible to produce an n-channel jfet connected in fixed bias configuration with a high gain of 200.

For your circuit, the product of the small-signal transconductance and drain impedance at the operating point set an upper bound on the voltage gain.

Using the numbers @Andy aka provides:

\$A_v < 20k\Omega \times 6.5 \frac{mA}{V} = 130\$

Since your drain resistor and load are in parallel with the small-signal drain impedance, your circuit gain must be less than this upper bound.

So, as a first step, you must select a transistor with maximum possible voltage gain quite larger than 200.

Edit: For a derivation of the JFET equation from physical principles, there are plenty of online resources. Google: "JFET device physics" and, for example, find this. The derivation is not trivial.

I'm not sure where you're getting your information but \$I_{DSS}\$ isn't given by the equation you've written. The following is from Marshall Leach's JFET notes:

In the saturation region of operation, the JFET total drain current is given by:

\$i_D = \beta (v_{GS} - V_{TO})^2\$ for \$v_{GS}> V_{TO} \$

Here, \$V_{TO}\$, the threshold or pinch-off voltage, is negative.

This can be written as:

\$i_D = I_{DSS}(1 - \dfrac{v_{GS}}{V_{TO}})^2\$

From the above, it is clear that \$i_D = I_{DSS} \$ when \$v_{GS} = 0 \$; it is the drain current when the gate and source have the same voltage.

Solving for \$I_{DSS} \$ gives:

\$I_{DSS} = \beta V_{TO}^2\$