I have an entity dummy
with an input port signal of type std_logic_vector
:
entity dummy is
generic (
LENGTH : natural);
port (
A : in std_logic_vector (LENGTH - 1 downto 0);
Q : out std_logic);
end entity;
When instantiating dummy
, is it allowed to associate A
with (others => x)
, where x
is a signal of type std_logic
?
dummy_i: entity work.dummy
generic map (
LENGTH => 4)
port map (
A => (others => x),
Q => open);
ModelSim 10.7b stops with the error message
** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 0 (-1 downto 0 (null array))
It works, however, if
- I use
(others => '0')
instead of(others => x)
(replace #1a with #1b), or - the length of port signal
A
of entitydummy
does not depend on the generic (replace #2a with #2b).
Full MWE:
library ieee;
use ieee.std_logic_1164.all;
entity dummy is
generic (
LENGTH : natural);
port (
A : in std_logic_vector (LENGTH - 1 downto 0); -- #2a
--A : in std_logic_vector (3 downto 0); -- #2b
Q : out std_logic);
end entity;
architecture rtl of dummy is
begin
Q <= '0';
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity modelsim_others_bug_testbench is
end modelsim_others_bug_testbench;
architecture rtl of modelsim_others_bug_testbench is
signal x : std_logic;
begin
x <= '0';
dummy_i: entity work.dummy
generic map (
LENGTH => 4)
port map (
A => (others => x), -- #1a
--A => (others => '0'), -- #1b
Q => open);
end architecture;
```
Best Answer
Prior to VHDL-2008: You cannot perform such action :
A => (others => x)
because this line is seen as an operation and that is not possible in an instantiation.(like in this post for example: Warning : Actual for formal port a is neither a static name nor a globally static expression)
However, there is a way to work around that, you have to create a new signal
y
:Notice that when copy/pasting your code on Vivado, the error is:
Actual for formal port a is neither a static name nor a globally static expression
I let you modify your code so that you can use the generic
LENGTH
.With VHDL-2008:
If look in the norm: http://www.fis.agh.edu.pl/~skoczen/hdl/ieee_std/ieee1076-2008.pdf You can find on paragraph 6.5.6.3 Port clauses:
In other word, in VHDL-2008, the code you provided works (I have no error using it with Vivado 2018.1, simulation works as expected)