mosfet
I don't understand why the gate charge curve (exactly: the Miller plateau part) of MOSFETs is dependent on the drain-source voltage Vds.
As an example, the datasheet of of the IRFZ44 shows on page 4 (Fig. 6) the gate charge curves for different Vds values.
Why is the Miller plateau longer for bigger Vds? Isn't the plateau dependent upon Cgd? But Cgd (= Crss) gets smaller for bigger Vds (see FIg.5 in datasheet).
Shouldn't the Miller plateau get shorter?
In the IR document, they are driving the gate with a constant current. See the test circuit:
That is, they are delivering a constant amount of charge per unit of time. That's why they have the same shape: if charge is a linear function of time, then they are basically the same graph.
Notice that the flat spot on the gate voltage graph corresponds to the period where the drain voltage is decreasing (\$t_2\$ to \$t_3\$). Perhaps the best explanation of what's happening here is the next chapter in the IR document you reference, the section on \$dv/dt\$ capability:
Here, they are showing what happens when the drain has an increasing voltage ramp applied. But, this works in reverse, also. When the drain voltage is going down, there must necessarilly be some current in \$C_{GD}\$, in the opposite direction. This is because, as with all capacitors, a change in voltage must be accompanied with a current:
$$ I = C\frac{\mathrm{d}V}{\mathrm{d}t} $$
So as the MOSFET begins to conduct, and the drain voltage begins to decrease, some of the current from the gate driver must go into \$C_{GD}\$ to decrease its voltage. This is current that can't be going into \$C_{GS}\$ to increase its voltage. Thus, for as long as the drain voltage is going down, the gate voltage barely increases.
At \$t_3\$, the gate driver has managed to get the drain voltage about as low as it can go. After this point, the drain voltage doesn't decrease much with increased gate charge. Instead, you get a relatively slow decrease in channel resistance. So now the charge going into the gate is free to go mostly into charging \$C_{GS}\$, and the gate voltage can rise rapidly again.
I've not heard the term Miller plateau until now, but I have heard of the Miller effect, which is essentially what I just described, but in the general case for all amplifiers. So, I can see how one would reasonably call that flat region the Miller plateau.
Further reading: Vishay - Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance addresses this topic in more detail, and specifically uses the term Miller plateau.
Sorry, but you're interpreting it wrong. The 63 nC is a maximum figure, while your graph shows typical Qg - which is, as you might expect, less than the maximum.
Best Answer
"Why is the Miller Plateau longer for bigger \$V_{\text{ds}}\$? "
The short answer is that Miller Plateau width scales with the area under the curve for \$C_{\text{gd}}\$. But why?
What does the Miller Plateau show?
The Miller effect exists because there is effective capacitance between the drain and gate of the FET (\$C_ {\text {gd}}\$), the so called Miller capacitance. The curve of Figure 6 in the datasheet is generated by switching the FET on with a constant current into the gate, while the drain has been pulled up through a current limiting circuit to some voltage \$V_ {\text {dd}}\$. After the gate voltage rises past the threshold and drain current reaches it limit (set by the current limiting circuit), \$V_ {\text {ds}}\$ starts to fall, displacing charge on \$C_ {\text {gd}}\$ through the gate. While \$V_ {\text {ds}}\$ falls to zero volts, from \$V_ {\text {dd}}\$, \$V_G\$ is stuck by the displacement current from \$C_ {\text {gd}}\$ ... that' s the Miller Plateau.
The Miller Plateau shows the amount of charge in \$C_ {\text {gd}}\$ by its width. For a given FET the width of the Miller Plateau is a function of the voltage traversed by \$V_ {\text {ds}}\$ as it switches on. The figure shows \$V_G\$ aligned with \$V_ {\text {ds}}\$ to make this clear.
The gate charge curve for the IRFZ44 shows three spans of \$V_{\text{ds}}\$; Span1 is 0V to 11V, Span2 is 0V to 28V, and Span3 is 0V to 44V. Now, some things should be clear:
Do these conclusions seem too hand wavy and snake oily to you? Ok, then how about this?
Why the Miller Plateau gets Wider for Higher \$V_{\text{ds}}\$ -- A Quantitative Look
Start with the equation for charge on a capacitor:
Q = CV with a differential form dQ = C dV
Now \$C_{\text{gd}}\$ is not a constant, but some function of \$V_{\text{ds}}\$. Looking at the curve in Figure 5 of the IRFZ44 data sheet for \$C_{\text{gd}}\$, we want some equation that is not infinity at zero \$V_{\text{ds}}\$ and falls off exponentially (ish). I won't go into any details here about how this was done. Just choose very simple forms that seem to match and try fitting them to the data. So, not based on device physics, but just matches pretty good with pretty little effort. Sometimes that's all that's required.
\$C_{\text{gd}}\$ = \$\frac{C_{\text{gdo}}}{k_c \text{V}_{\text{ds}}+1}\$
where
\$C_{\text{gdo}}\$ = 1056 pF
\$k_c\$ = 0.41 -- an arbitrary scaling coefficient
Checking this fitted model to the datasheet we see:
\begin{array}{ccc} V_{\text{ds}} & C_{\text{gd}}\text{(data)} & C_{\text{gd}}\text{(model)} \\ \text{1V} & 750pF & 749pF \\ \text{8V} & 250pF & 247pF \\ \text{25V} & 88pF & 94pF \end{array}
So, after plugging the \$C_{\text{gd}}\$ model expression into the differential form of the charge equation, and integrating both sides we get:
Q = \$\frac{C_{\text{gdo}} \log \left(k_c V_{\text{ds}}+1\right)}{k_c}\$ = \$\frac{\text{1056 pF } \log \left(\text{0.41 } V_{\text{ds}}+1\right)}{\text{0.41 }}\$
A plot of Q shows that it always increases for larger changes of \$V_{\text{ds}}\$.
The only way this would not be true would be if \$C_{\text{gd}}\$ became negative for some values of \$V_{\text{ds}}\$, which isn't physically realizable. So, more is more.