Electronic – Is there difference between Timer vs Counter in ATmega328P

On the PICs with two 32KHz timers (TMR1 and TMR3) my recommendation would be to use one of the timers 'free-running' (never write to it) and use the other to generate wakeup events. If you only have one timer available, getting reliable operation without cumulative errors is going to be very difficult. Different part revisions have different behaviors when it comes to writing timer 1, and so an approach that would work with one revision may be broken by a future revision. What would have been nice would have been if Microchip had allowed the timer to switch between synchronous and asynchronous modes without losing a count (simple to do: instead of using a multiplexer to switch between sync and async mode, add asynchronous set/clear to the synchronizing latch, and when in async mode use those to force the output to follow the input). None of their parts are, so far as I know, documented as doing any such thing. Consequently, I would expect that switching between synchronous and async mode may randomly gain or lose a count.

Peripherals like timers and Usarts get their clocks via the APB prescalers. The Interface Clock is at the prescaled frequency, used for sequencing most peripheral functions. APB1 has a max allowed value of 42MHz, APB2 max 84 MHz.

The Timers have an oddity where the frequency fed to the clock input of the Timer Prescalers, when the APB prescaler is NOT /1, is twice the corresponding Interface Clock. Thus, when the SysClk is at the max of 168 Mhz, APB2 is prescaled by 2 to get 84 MHz, the Timers driven from APB1 get twice that, 168 MHz, into their prescalers . Same logic for APB1, /4 => 42 MHz i/f, *2 => 84 MHz => Timer prescalers.