It is very likely CPU's and SoC's are used by hardware description languages like Verilog and VHDL (two major players).
These languages allow different levels of abstractions. In VHDL, you can define logic blocks as entities; it contains inputs and output ports. Within the block you can define the logic required. Say you define a block with input A, input B and output C. You could easily write C = A and B;, and basically you created a AND port block. This is possibly the simplest block you can imagine.
Digital systems are typically designed with a strong hierarchy. One may start 'top-level' with major functions a CPU requires: proccesor (multiple?) memory, PCI-express, and other busses. Within this level busses and communication signals between memory and procesor may already be defined.
When you step one level down, it will define the innerworkings of making something 'work'. Taken an example of a microcontroller, it may contain an UART interface. The actual logic required to make a functional UART is defined one level below.. In here, much other logic may be required to generate and divide the required clock, buffer data (FIFO buffers), report data to the CPU (some kind of bus system).
The interesting thing of VHDL and digital design is the reuse of blocks. You could for example, just copy&paste the UART block in your top-level to create 2 UARTs (well, maybe not that easy, only if the UART block is capable of somekind of addressing!).
This design isn't any kind of gate-level design. The VHDL can be also be 'compiled' in a way that it is finally translated to logic gates. A machine can optimize this far better than a human could (and quicker too).
For example; the internals of block A requires an inverter before outputting the signal. Block B takes this output signal and inverts it once again. Well, 2 inverters in series don't do much right? Correct, so you can just as well leave them out. However, in the 'top-level' design you won't be able to spot the two inverters in series.. you just see two ports connected. A compiler can optimize this far quicker than a human.
Basically what digital system design contains is the description how the logic should 'behave', and the computer is used to figure out what the most efficient way is to lay out the individual logic gates.
Both. And there's quite frequently a team of hundreds involved; the latest Intel flagship processor will probably have had over a thousand people involved in design decisions somewhere (especially if you count technical input from the foundry, which is vital if you're using a new manufacturing process).
Generally the process involves:
- high level architecture design, by humans
- implementing the design in Verilog and/or VHDL, by humans
- translating that into logic gates, by software
- placing the gates and routing wires between them (software with constraints and guidance by humans)
- analyse the result (software) and review key areas for improvement (by humans)
- translate gates to images for photomasks (represented in the "GDS II" file format)
- generate test data (software-assisted humans)
- manufacturing and test process (mostly automated)
Edit: there are also lots of things which up the transistor count without having to design them all individually; SRAM, for example, is a large grid of repeating elements. The A7 will have a substantial fraction, maybe a majority, of its transistors devoted to L1 and L2 cache.
Best Answer
The Address and CE# pins are quite heavily loaded, as are the data pins during a write. Even though only a single device is active at any time, the capacitive load of the pins is present from all devices at all times.
From the datasheet, A0 to A19 will have up to 48pF load plus any track capacitance and the data pins will have up to 64pF during write. CE# has a slightly heavier load (by virtue of driving the '38 decoder as well as all the memory devices).
That is a bit hefty (equivalent to about 40 inches of 4 thou track for the address pins and almost 60 inches of track for the data pins), so you may wish to consider Address and Data buffers. The track capacitance assumes a 4 thou PCB core to plane.
As noted, you will also need decoupling: a couple of bulk capacitors and two 100nF per device (one for each power pin as they are on opposing sides of the memory devices) would be my starting point. The decoder would probably be ok with a single 100nF part.
You may not need all of the decouplers, but if the pad positions are there, you can always choose to simply not fit the parts.
You may be ok with a single power pin (only one device will be active at any one time), but I would normally provision at least 2 if I have enough pins available.
Update: Use of CE# signal.
As the second SRAM CS signal is being gated by CE# already, it seems redundant to take it to the SRAMS as it is doing the same thing and layout can be simplified.
I would just tie off that CE# signal low at the SRAMS and use the gated and decoded CS.
This has an added benefit: as the capacitive loading on CE# has been significantly reduced, a great deal of timing uncertainty has been removed.