As a general guideline, it is preferable to connect any cable shields to the metal chassis (not PCB ground), at just one end. To keep things simple when multiple shielded cables connect out from some central device, the shield connection should be done only at the "hub" device, and left open at the "spoke" devices.

Similarly, for a chain of devices connected by shielded cable, each shield ought to be connected to the chassis of the upstream device, and left open at the downstream end. Yes, this does mean that the shields of different links of such a chain might be at different potentials, depending on how well earthed the individual devices are, but this is generally not a problem.

A basic, inexpensive addition incorporated in many consumer device cables today, is a clamp-on ferrite bead or "split bead" at each end of the cable, close to the connector. This reduces high frequency EMI off the shield with minimal complexity. A good document about such RFI beads is here.

Note that the chassis is usually connected to "earth" of the location, not to ground of your circuit board.

Of course, this is a simplification of a fairly complex subject, but it serves the purpose for designs at frequencies where surface effects do not predominate. As frequency of signals involved rises into GHz, other factors need addressing.

From the datasheet:

2.2.1 Clock Generation

The TAS1020B requires an external 6-MHz crystal with load capacitors and PLL loop filter components to derive all the clocks needed for both USB and codec operation. Figure 4-1 shows the connection of these components to the TAS1020B. Figure 4-1 also shows a ground shield residing on the top layer of the PCB and underneath the crystal and its load capacitors and the PLL components. The PLL is an analog PLL, and noise pickup in these components can translate to phase jitter at the output of the PLL, which in turn can translate to distortion at the codec. A ground shield is recommended to attenuate the digital noise components on the board as seen at the PLL.

The AVSS and AVDD pins on the TAS1020B are used exclusively to power the analog PLL. To maintain isolation from the digital noise residing on a board, AVSS should be a separate ground plane that connects to the primary ground plane (DGND) at a single point via a ferrite bead. The ferrite bead should exhibit around 9 Ω of impedance at 100 MHz. AVDD should also be distinct from DVDD. A recommended architecture is to generate DVDD and AVDD from the same regulator line, with each derived from a RC filter in series with the regulator output. It is finally recommended that the ground shield for the crystal and its load capacitors and the PLL loop filter components be connected to AVSS at a single point via a ferrite bead of the same type as above.

Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internally in the TAS1020B is a major advantage with regard to EMI.

(emphasis mine)

So it's basically suggesting that you should put a copper filled polygon on the top layer underneath the crystal and it's load capacitors and connect it to your analog ground via a ferrite bead in order to provide a low impedance current return path to reduce jitter on the PLL.