Could anyone tell me if JTAG requires to have the same bus(wire) length for TDI, TDO, TMS, and TCK?
Electronic – JTAG Bus Length
debuggingjtag
Related Solutions
I don't know the exact reasoning for JTAG, but when high speed signals are used and according to the best practices, you should put a GND in between every signal of a flat cable. JTAG can be considered as a High Speed Signal.
Multiple GND wires are used to avoid crosstalk between the signal lines. They avoid capacitive coupling between adjacent lines. And they also provide a separate return path for every signal. Indeed, in high speed signals, the return current "prefers" the path of least impedance. That path is, for high speed signals, the closest GND. Thus the different signals will have different return paths and that avoids crosstalk of the return path.
The final goal is to guarantee good signal integrity, reduced emissions and a better immunity to external disturbances.
Taken from a Segger web page:
1 VTref Input This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2 Not connected NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.
3 nTRST Output JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unin- tentional resets when there is no connection.
5 TDI Output JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.
7 TMS Output JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of target CPU.
9 TCK Output JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.
11 RTCK Input Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13 TDO Input JTAG data output from target CPU. Typically connected to TDO of target CPU.
15 RESET I/O Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
17 DBGRQ NC This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
19 5V-Target supply Output This pin can be used to supply power to the target hardware.
Best Answer
Although you should pay attention to the datasheet and general signal integrity issues with the signals, no, they don't have to be exactly the same length.
Many programmers allow you to slow down the clock rate if you are having issues anyway - just make sure you read the literature for whatever it is you are designing for.