Electronic – Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

amplifiercadencedramlatch

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it drives one input to VDD and the other to gnd. I don't know why the pass transistors are always in region 0. These are the waveforms I get I don't know where the problem is or what solutions should I think of..

Latch_based SA design[![Waveforms]2

Best Answer

Your pass transistor is in cutoff because your Vgs is much greater than your Vth.

Also, how exactly are you expecting the SA to operate? Wouldnt you want OUT1 and OUT2 to be complements of each other since its a cross coupled inverter?