latencylogic-gatessystem-verilogverilog
today I learn about latency especially Tpdhl (high to low) and Tpdlh (low to high).
My question is, let's suppose a gate has Tpdhl=8 and Tpdlh=6 so how much time it will take to process the input if it was uninitialised at first?
Does that rely on the input if it's 0 or 1? please help me
CL minimum value is time based, but it is counted in clock cycles. So using it at a lower frequency you can presumably reduce CL - but if so, you must specify the actual CL value in the DRAM's mode register on initialisation; if the data sheet gives a mode reg bit pattern representing CL=5, then you are probably OK.
Also check that your reduced clock frequency is still within the permitted range for the part's internal DLL (there will be a minimum freq specified) but I think 270 MHz will be OK.
These details are from memory, but I did reliably operate DDR2 from a Virtex-5 FPGA at just under 200MHz so there is some leeway.
It sounds like you want something more along the lines of a monostable multivibrator. For example, the 74HC123. This device produces a pulse of a set length when it receives an input.
The internal schematic for 1/2 the device (it's a dual) is shown here:
You can see that there are internal feedback paths (the cross-coupled NAND gates) that allow it to retain states while the external RC circuit operates.
You can treat this as a black box with this behavior:
Best Answer
These delays assume a known state. There is no such thing as an uninitialized in real hardware, but if you are asking how simulation in Verilog/SystemVerilog interprets it; X→1 is a rise, X→0 is a fall.