Electronic – Limitations of MOSFET-pair Current Mirrors

currentcurrent-mirrormosfet

schematic

simulate this circuit – Schematic created using CircuitLab

For simple MOSFET-pair current mirrors, such as the NMOS version above, are there any known disadvantages that one has to consider? The above example, for instance, does not perfectly mirror the current (I really don't know about this, as the LTSpice sim works perfectly).

I'm excluding the discussion about parameter mismatch between the MOSFET pairs (V_TO, λ, K, etc)and the condition I_REF ≤ V1/R_LOAD, but more of noise or bias or anything like that.

What I mean is does this just sorta average out as current mirroring? The same way that a Common Drain sorta averages out as having voltage gain of a little less than unity?

EDIT:

What about frequency response? Can MOSFET-pair Current Mirrors reach GHz range?
Or, Is it useless to ask? This being the simplest MOSFET-based Current Mirror?

Best Answer

One of the reasons could be that since you have an extra load the resistance of the right side is different compared to the left side mirror. So this would cause slight deviation in the mirrored current. Or the mosfet to the right is not in saturation ! Because 100ma is a lot of current and the voltage that it would create at the gate of the left side Mosfet would be high such that Vds of rights side mosfet is small compared to Vgs (Since the same Vgs is given to the right mosfet) therby putting the right mosfet in the triode region. Checck if the mosfets are in saturation first , if they are then the deviation would be purely because of differnces in Vds from the 2 transistors.