I was watching one of Jacob Baker's videos
(http://cmosedu.com/videos/f10/ece5472/lec1_ece5472_video/lec1_ece5472_video.html)
At minute 19:30, he explains the concept behind linear regulation:
His Explanation
He explains it by saying that if the output regulated node is at 1.9V and reference is 1.8V, then the gate of the PMOS device will increase, decreasing current in the branch and a smaller voltage drop across the load resistor hence the output regulated voltage goes down to 1.8V.
My Explanation
The way I see it is that if the gate of the PMOS device goes up and if I follow this graph:
Then we would switch to a Vgs curve which has a less steep slope and thus the PMOS device would actually have a higher resistance, dropping a larger voltage and thus bringing output node down to 1.8V.
Is my understanding valid? (I hate thinking of PMOS devices as fixed resistors(like a lot of authors simplify it to be) since it doesn't satisfy KVL).
Best Answer
His explanation is "correct enough" but less clear than it could be.
Your explanation is also "correct enough", but the use of the transfer function curves add more complexity than is needed for a basic explanation.
A basic statement, which is reflected in the transfer function curves is
"A PMOS transistor will exhibit decreasing drain-source resistance as the gate is driven more negative relative to the source".
The opposite also applies - making the gate less negative relative to the source increases Rds.
With the above basic concept to work with, the regulator operates by
increasing Rds if Vout is too high,
and reducing Rds if Vout is too low.
Rds and Rload form a voltage divider that cause the above action to drive Vout in the correct direction.
In the circuit in question the opamp / comparator is arranged so that if Vout is > Vref then Vgate is driven higher so |Vgs| decreases so Rds increases so Vout decreases.
Is that easier to understand?
[Explanations that seem simple to one person may not appear simple to another].