I'm designing a PCB with some noise-sensitive components (FPGA, RF mixer, etc.). For the power systems I've decided to chain switching regulators to LDO regulators so that I get less heat dissipation and better noise performance than either alone. However, I'm unsure as to the optimal location of the LDO regulators. My thought is that they should be placed near the outputs of their corresponding switching regulators so that switching noise is confined to the edge of the board. Or is it better to place them near the loads they drive? The second setup could result in a slightly more accurate voltage across the load since less of the LDO output voltage will drop across the power traces, but since my board isn't too big and I have room to make the power traces wider if need be, I'm not too worried about that. I'm also not too worried about trace inductance because the bypass capacitors should take care of that.
What else am I not considering here? Is there a typical way this is done?
Best Answer
LDOs regulate output voltage relative to their own GND pin, and the capacitor which is usually placed right at the output for stability will link the local GND with the output at HF too. So if you have substantial current in your ground plane, GND may not be the same voltage everywhere. Just like voltage drop from trace resistance, this is an argument to place the LDO closer to the load.
It is very important to not screw up the switchers layout also.
Now you have to consider each load both as a potential victim of noise ingress but also as a noise generator. So, for each load consider current and voltage but also noise tolerance at various frequencies, etc. Then, consider the current that is drawn by the load, is it constant, spiky, random, HF, etc?
Each load will be sensitive (to various degrees) to supply ripple and noise, but each load will also generate ripple and noise on its supply.
This also depends on the time scale. For example, if you got USB2 then there is a chip in your design that will draw current spikes at 8kHz each time it processes a packet. Average current draw will be constant but the power rails of this chip will have 8kHz ripple. If you check the analog output of some USB soundcards... you will very often find some garbage at 8kHz, and if you're lucky, the signal may even intermodulate with the 8kHz stuff, like if the DAC reference voltage is a bit too friendly with the power supply of the USB chip.
A crystal oscillator can draw constant average current (the switching spikes are averaged by the local decoupling cap) but it might turn power supply noise into phase noise.
Then you can split it into power domains, and fence these with ferrite beads or use several LDOs. It depends a lot on the noise frequency bands.
For example if you have a 5V switcher supplying both:
In this case we connect the micro to the switcher output. And, since the opamp will reject LF noise and supply ripple well, it doesn't care if we add an extra ohm in its power supply line. If it draws a variable current of a few tens of mA, then it will wobble its own supply by a few tens mV, if it has 80dB PSRR at that frequency, that's no concern. So this opamp doesn't need a local LDO, however it needs a supply without HF noise on it, which means a ferrite bead in its power supply with a local decoupling cap (make sure these don't resonate).
So try to keep this in mind, group loads on power domains by how well they will work together, then apply LC filters where needed to prevent cross-contamination, then decide how many LDOs you need.
LC filters block high frequency noise, but let LF noise through. Your LC filter will usually be a Pi filter since there will most likely be a cap on both sides of the ferrite bead... which means it prevents HF noise from getting into the load, but it also prevents HF noise generated by the load from contaminating the main supply. The local decoupling caps provide a small loop for HF current and the ferrite adds impedance to make sure HF load current doesn't go where you don't want it to.
LDOs remove low-frequency ripple and noise, but at HF the pass transistor is a capacitor, so HF noise goes through. Parasitic capacitance increases as dropout voltage decreases, so higher efficiency means worse HF PSRR. Also, the LDO draws its current from the supply, so it passes on variable load current to the main supply. This is only at LF though, so less of a problem.
To remove both frequency bands, you can use a LC filter followed by a LDO.
A few cents in LC passives plus a cheap LDO may have higher PSRR than a high-end, "high HF PSRR" LDO. And passives are the only solution to get decent rejection above 10MHz.
A high current filter right at the output of the switcher may not be the ideal solution. Maybe your FPGA draws lots of current on 3V3 VCCIO but it doesn't care about the noise. So you can use a much smaller cheaper low current filter just for the sensitive parts on 3V3, like the clock or whatever. Beads perform better at low DC current, less core saturation.