Electronic – LNA design question – series drain inductor

amplifiercadencedesign

I am designing an LNA in Cadence that follows the schematic below very closely. This is taken directly from TH Lee's book on RF integrated circuit design.

The book says that \$L_d\$ and \$C_L\$ should be tuned to resonate at the center frequency of the design. So in terms of small signals, the drain of M2 should see a very high impedance.

I am trying to understand how the DC levels in this circuit work. Because \$L_d\$ is essentially a short circuit to Vdd, the drain of M2 sits right at VDD. How is there any headroom for voltage gain when the DC drain voltage of M2 is equal to Vdd?

LNA_schematic

Best Answer

How is there any headroom for voltage gain when the DC drain voltage of M2 is equal to Vdd?

Plenty of amplifiers have inductors tying drain or collector to Vcc - all it means is that the average voltage on the drain must equal Vcc - it doesn't stop an AC signal being superimposed on top of the DC level at the drain.

Think about how this transformer connected common-emitter amplifier works: -

enter image description here

You could say that the transformer primary shorted the collector to Vcc but that's only at DC - the AC signal sits on the collector (at Vcc) quite happily. The collector voltage rises to nearly twice the peak of Vcc and falls to nearly zero volts.