Electronic – Low power amplifier for 433MHz wake up receiver

low-powerreceiverwake-on-radio

I’m designing a low power wakeup receiver (WuRx) circuit that will be used to wake up an Arduino and its 433 MHz transceiver, both of which pull way too much current (tens of milliamps) to keep running at each remote node. The goal is to develop a low power wake up receiver / detector that will wake up Arduino (or any sleeping MCU) when RF wake up signal is present. The RF wake up signal will be a series of brief OOK pulses from the transmitter.

I need to amplify the UHF signal from its ten microvolt antenna level, to at least 100 millivolt to 1 volt level in order to detect the RF envelope via a simple diode rectifier, which will then trip a comparator indicating “RF present” during OOK (on-off keying). These pulses will then be counted using some flip/flops or a counter within a given time window to detect a valid wake up signal.

I have done extensive research on these wake up receivers and prior art. Traditional conversion of RF to IF results in too much quiescent current due to the LO current. This has led me to conclude that a low power RF amp fed by a ceramic bandpass filter can solve this problem.

Since this is simply an RF wake up detector, linearity during amplification is much less important than very low quiescent current when no RF is present. These IoT style slave sensors typically sit idle 99.999% of the time, only needing to awaken for a few tens of milliseconds whenever the master polls them.

The flow will look something like this:

Antenna -> Bandpass Filter -> RF Amp -> OOK Envelope Detector -> Wakeup Interrupt to Arduino -> Transceiver Wakeup -> Rx Data -> Process Rx Data -> Back to Sleep

My problem is how to minimize the quiescent amplifier current drain (to nanoamp level ideally) yet sufficiently amplify the microvolt signal once its present and coming out of the bandpass filter. Total amplifier current drain when RF signal is present can be a few milliamps. I’m thinking several 15 dB to 20 dB amplification stages in series to yield a 10,000 to 100,000 x signal boost should be sufficient; e.g. 10 uV to 100mV – 1V.

I’m looking at LNA transistors like the BFP720, a low noise silicon germanium BJT, but willing to consider all low cost options. Low cost and small footprint are also factors but low quiescent current consumption on 3V battery power is critical.

I’ve tried Class C amplifiers with resonant circuits but simulations are failing (using SystemVision simulator) due to low (millivolt) level input signals being too tiny to allow the transistor to conduct. What type of amplifier can I use that has very low quiesce bias current and can amplify this tiny UHF signal?

If I can figure this out, it will help a lot of folks out who are struggling to solve this type of low power wake up problem.

Thanks in advance for guidance.

Best Answer

This is another "not an answer" :) I do not have enough experience to suggest a circuit.

There are hundreds of very low power (down to 300 nA) single-supply Op Amps. Have you considered these instead of transistors?

Furthermore, the same Op Amp can become part of active bandpass filter, reducing number of components and possible power draw too.

UPDATE

Re address decoding, here is an idea of a protocol that should be easy to implement with simple logic components:

  • The transmitter encodes target address as follows:
    1. Node IDs are selected from a subset of natural numbers with less consecutive "1"s than chosen "trigger" length. Let's say trigger is 4 bit long.
    2. "0" is transmitted, followed by node ID, using pulses of two different lengths. Let's say long pulse for "1" and short for "0".
    3. "0" is transmitted, followed by the "trigger" as group of "1"s, e.g. "01111"
    4. Note that transmission frequency is constant, so shorter pulses are followed by longer pauses and v.v.
  • The receiver is connected to monostable multivibrator triggered by rising edge of a signal. Multivibrator generates pulse that is longer than "0" and shorter than "1".
  • The falling edge of the multivibrator is used as clock for shift register, while the receiver output is used as data input.
    1. The end result is that shift register contains node ID, 0 and the trigger.
    2. At no time the register has 4 consecutive "1"s until entire packet is received.
  • The trigger bits of a register are connected to AND gate. The address bits are compared to address selection DIP switch with XNOR (or XOR, does not matter) gates and the outputs are fed to the same AND gate. The output of the gate is wake-up signal.

This approach has the benefit of fixed packet length and no need for synchronous clock. 8-bit address can be implemented with as few as 3-4 ICs. Below is simplified diagram.

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The output can be used as wake-up or to control power switch. With power switch MCU will be running until you send a different address. With wake up you can add "waiting time" to MCU logic then wake up several of them and transmit to all of them simultaneously.

Oh, and all the signals can be inverted, of course. For example the presence of RF carrier can be used to power-up decoding logic and then Off pulses will transmit the address.

UPDATE 2

I was in the process of typing some additional thoughts when I saw that link in the comments. Very interesting read indeed, by itself and some references too. It has helped those thoughts to crystallize into these key design points:

  • For this application the design of the RF stage is just as important as selection of the low-power components. All the known tricks to maximize antenna gain should be used. For example, directional antenna increases reception from the master node while at the same time significantly reduces interference, thus minimizing false wake-ups.

  • Staged power management. This means breaking signal processing into multiple steps by power requirements so that the power to next stage is only applied when the signal conforms the criteria of the previous stage. I am not particularly impressed by the use of comparator and SPI interface in the article. They both require power too early in the processing chain. Just as they use preamble to generate wake-up for the processor, the presence of RF carrier for a certain period can be used as criteria for powering up the comparator. The output from comparator and preamble detector can be used to power up address decoding logic, and so on.

  • Integrated RF signal. Voltage doubler is good, but why stop there? It could be possible to use multiple diodes or MOSFETs to build charge pump with enough power to satisfy your distance requirements. The basic idea here is that sacrificing data rate by increasing pulse duration allows RF stage to build-up voltage to useful levels. This also means inverted OOK modulation (i.e. using pauses as data pulses) is preferable. Also, as low as power consumption of MCU can be, the address detection with logic chips might still be more efficient, and can be done faster (MCUs typically require hundreds of cycles to wake up from deep sleep).

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