Let's say we have the following netlist
* Standard cell circuit
.global VDD VSS
.prot
.lib '.\reference_models.lib' TT
.unprot
***********************************************************
.SUBCKT ZP_NAND2 QN A B
M1I1 N1N9 B VSS VSS N W=WN L=LN
M1I2 QN A N1N9 VSS N W=WN L=LN
M1I3 QN A VDD VDD P W=WP L=LP
M1I4 QN B VDD VDD P W=WP L=LP
.ENDS
.SUBCKT ZP_INV QN A
M1I1 QN A VDD VDD P W=WP L=LP
M1I2 QN A VSS VSS N W=WN L=LN
.ENDS
.SUBCKT AN2D1 Z A1 A2
X1I8 N1N1 A1 A2 ZP_NAND2 wp=1.62um lp=0.35um wn=1.07um ln=0.09um
X1I9 Z N1N1 ZP_INV wp=2.70um lp=0.35um wn=1.35um ln=0.09um
c1 Z VSS 0.018pf
c2 A1 VSS 0.009pf
c3 A2 VSS 0.009pf
.ENDS
**************************************************************
X1 Z A1 A2 AN2D1
*************************
.param vdd = 1.8
.param vss =0
Vvdd VDD 0 VDD
Vvss VSS 0 VSS
Vin1 A1 0 pulse (vss vdd 2ns 200ps 200ps 3.8ns 8ns)
Vin2 A2 0 pulse (vdd vss 4ns 200ps 200ps 2ns 8ns)
.TRAN 1p 20n
.measure tran pow_avg_X1 avg p(X1)
*.measure tran pow_avg_mn avg p(X1.mn)
*.measure tran pow_avg_mp avg p(X1.mp)
*.measure tran total_power param='(pow_avg_mn+pow_avg_mp)'
.measure tran I_integ integ I(Vvdd)
.measure tran P_Iinteg param='I_integ*vdd/20n'
****************************************************
.meas tran TPHL trig v(A2) val='0.9' TD=0
+ fall=1 targ v(z) val='0.9' fall=1
.meas tran TPLH trig v(z) val='0.9' TD=0
+ rise=1 targ v(A1) val='0.9' rise=1
********************************************************
.end
When we run it in hspice, we get the following result for Tplh and Tphl
tphl= 1.1032E-10
tplh= -6.6974E-11
How do we make them equal(not necessarily 100% equal,, but lets give them a maximum difference of only 3%)? The only thing that we can vary is the transistor's width (we need to make the 'L' fixed to 90 nm). Aside from randomly guessing the value of 'W' to make them equal, are there any methodologies out there to follow?
Thanks
Best Answer
There is no need for guessing, but you will need to look at the transistors data-sheet for \$I_DS,Sat \$ per width, and you should understand what happens when you stack transistors.
Alternatively, you can set the \$ \dfrac{G_m}{C} \$ for the NMOS and the PMOS to be the same.
I will note several odd things with your netlist: