I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of starting execution of the Extender , is dependent on the control logic , can anyone explain this misunderstanding ?
Electronic – misunderstanding of a Computer Architecture
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Given the goals of the class, I think the TTL approach is fine, and I say this as an "FPGA guy". FPGAs are a sea of logic and you can do all sorts of fun stuff with them, but there's only so much that's humanly possible to do in a semester.
Looking at your syllabus, your class is a mix of the logic design and "machine structures" courses I took in undergrad. (Plus, it's for CS majors. I'm all for CS majors having to face real hardware--letting them get away with writing code seems like a step back.) At this introductory level, where you're going over how assembly instructions are broken down, I see no real benefit to having students do things in code versus by hand. Doing HDL means learning the HDL, learning how to write synthesizable HDL, and learning the IDE. This is a lot more conceptual complexity and re-abstraction. Plus you have to deal with software issues.
Generally the point of a course that uses FPGAs is to practice creating logic that is useful--useful for talking to peripherals, serial comms, RAM, video generators, etc. This is valuable knowledge to have, but it seems very much out of the scope of your course. More advanced classes in computer architecture have students implement sophisticated CPUs in FPGAs, but again, this seems out of the scope of your course.
I would at the very least devote a lecture to FPGAs. Run through a few demos with a dev board and show them the workflow. Since you're at Mills, perhaps you could contact the folks at Berkeley who run CS150/152 and go see how they do things.
You basically have two options here:
- A current-generation 486-based CPU
- Upside:
- Everything will likely be integrated into the main CPU - No southbridge, IO controllers, etc...
- you can actually buy the ICs off the shelf.
- Downside:
- Devices may be BGA
- few exposed busses
- may want to run at a few hundred Mhz.
- By "Currently Produced", I mean something like a AMD Geode, or similar device from VIA, etc... There is a pretty big market for small, low power, low speed x86 CPUs in embedded applications.
- Upside:
- A old-stock or old-design 386/486 CPU
- Upside:
- Probably more educational
- Downsides:
- Requires a LOT of devices (e.g. Southbridge, a UART, etc...), all of which are additional ICs.
- Note: the external devices will vary depending on which 386/486 you decide on. The early ones had few integrated peripherals. Later on, many of the peripherals got integrated into the CPU itself.
- Upside:
There are some midpoint-devices, like the 386EX, which is a 386 intended for embedded applications. It's old enough that it's available in TQFP-144 (released in 1994), yet it includes most of the necessary peripherals on-die.
Datasheet
Some resources, off the top of my head:
CoreBoot:
A FOSS BIOS alternative.
Interesting forum thread about building a IBM XT compatible computer.
Other stuff:
Dieter's Homepage
Some nutjob who build a discrete Transistor CPU!
He also has a bunch of other homemade CPU projects
Really, If I were you, I would go with an ARM device. You can get big ARM CPUs that have MMUs, and will run linux fine.
Alternatively, an 8088 or 8086 may be significantly more approachable. There is lots of information about people homebrewing 8088 computers out there.
Best Answer
The timing of the "Second ALU Input" depends on three things:
Yes, the labeling on the timing diagram is a bit unclear, but this is all they're saying. Either the path through the control logic or the path through the sign extender will be the long path that determines the final settling time for the second ALU input.
In static timing analysis, you need to take the worst case combination, and they seem to be implying that the worst case is the path through the control logic.