dc/dc convertermosfetringing
I am trying to choose a series resistor for a MOSFET (PSMN1R5-25YL) in order to reduce ringing, and I wish to know the guidelines for choosing the right resistance.
I'm not sure if it's relevant, but the application is two DC-DC converters, one is switched in 200KHz with 1A current from the gate drivers, and the other in 1MHz with 4A current from the gate drivers.
I'm going to ignore the reference to tetrode, I have never understood why an exact analogy reveals a fundamental truth.
The miller effect arises in situations from a connecting capacitance across two nodes that that have an inverting voltage gain/relationship between them. it doesn't have to be in transistors either, but in MOSFET's you have \$C_{GD}\$. How this is traditionally solved is to cascode the amplifier by isolating the offending capacitance so it doesn't appear across the gain stage. The dual gate Mosfet is basically a cascode stage with the cascode transistor built in (this has a secondary effect, see below), you just have to bias the the transistors so that they are in the active regime. M1 = amplifier, M2 = cascode
simulate this circuit – Schematic created using CircuitLab
The amplifer transistor converts the input voltage in the output current and the cascode transistor simply transfers this current to the output load. the output is on the drain of the cascode and the input is on the gate of the amplifier transistor. There is no capacitance across the two nodes, the miller effect is greatly reduced.
Cascoding greatly helps in gain too.
An interesting effect from manufacturing comes into play. The upper device is a longer gate device and the lower is a dual gate device. The S/D implant to channel capacitance tends to be lower than the S/D to isolation edge capacitance (the S/D's on the outer edge) so the S/D in between the gates will tend to have a lower capacitance that if you were to have designed the circuit using two separate transistors in a cascode configuration (and obviously they take up less area). This means that the \$C_{SB}\$ capacitance is less as well making for a higher speed circuit, here SB = Source to Bulk (AKA well).
If I understand you correctly, you're asking why \$R_1\$ (and \$R_2\$) in the following schematic is usually taken to be very large, right?
In summary:
if you take big resistors for Gate's biasing you get low power waste by these resistors + high input impedance of the amplifier.
Explanation:
The main function of these resistors is to form a voltage divider which defines the DC portion of Gate's voltage. This action is known as "biasing".
However, this does not answer why take such a high value resistors. You can form voltage divider with any resistors, as long as their proportion is correct. There are (at least) two reasons why you want these resistors to be big:
Best Answer
If you model the gate drive circuit as so:
simulate this circuit – Schematic created using CircuitLab
Where C1 is the gate capacitance of the MOSFET, L1 is the total inductance of the drive loop including package inductance, and R1 is the gate resistor plus resistance of the driver, then you can solve for the minimum value of the gate resistor that will result in a damped response that does not ring.
R1 \$\ge2\sqrt{\frac {L1}{C1}}\$
So if your input capacitance is 5nF, the loop inductance is 100nH,then R1 > 9\$\Omega\$ (subtract the minimum of the high/low driver resistances to get the minimum gate resistor).
In practice, you may not be able to predict the loop inductance all that accurately and you may have to select the exact value of the gate resistor empirically.