The schematic is an approximation of my circuit. I am trying to know when SW2 is closed. So I have a voltage divider there to detect it. But what happens is when V1 is activated both FETs conduct until the gate gets charged. This quickly charges C1. Now I'm dealing with the RC of C1 and the measurement voltage divider. Any suggestions on how to get a better reading of the status of SW2? This is a charging bus so I don't want to add too many components in the path if I can help it. Is there some way to prevent the brief activation of the FETs at powerup? Should I shrink R2? Oh and the measurement divider is actually an IC that is measuring so its probably even higher resistance than what I have shown. I can't change that.
simulate this circuit – Schematic created using CircuitLab
Best Answer
Although not the most elegant solution or sounds even counter-intuitive, adding a small capacitance (\$\approx 10nF\$) between the source and gate of the MOSFET will reduce their "unwanted turn on" at start up.
How would that work?
If the \$V_{th}\$ and gate capacitance of the MOSFETs are large enough, at start up, the \$V_1\$ supply voltage will try to charge them through the body diode of the MOSFET \$M_1\$ and \$R2\$. This behavior has also a dependency on the slew rate of the supply voltage. By adding a small capacitance between source and gate, you create a low-resistive path for high frequency signal (in this case the supply voltage at start up). This helps to pre-charge the gate capacitance.
As you can see in the simulation, the \$V_{GS}\$ of the MOSFETs is drastically reduced at turn on. The simulation is run for both cases, with (green line) and without (red line) the additional capacitance.
Here is a possible approach to your original circuit. You would have to check whether you have problems with hysteresis, but other than that it should do what you want. Furthermore, some diode is required at the output of your \$V_1\$ supply voltage in order to avoid back feeding.