The inputs of TTL logic gates are emitters of NPN transistors. They are current sources so when not connected they act as High level or logic "1", so your AND gate sees two high inputs, and naturally outputs a High. It is good practice to connect inputs you want to be high to the positive supply, either directly or through a resistor.
For the inputs to act as Lows, they must be connected to the negative side of the supply (normally considered "ground").
The above applies to 74xx, 74LS, and 74ALS logic families.
The CMOS logic families 74AC, 74C, 74HC (and anything else with a "C" in the middle) have very high impedance inputs which, if left unconnected, will assume random logic levels. With these parts, inputs must be connected to either supply or ground, either directly or through a resistor, and not left unconnected.
I think you're going into far too much detail too early on. I've designed complex state machines many years ago and this kind of problem is going to be a bit tricky to get right.
Step 1, is to get the behaviour right. Don't even think about assigning binary numbers to represent the states yet. Clearly from your postings, you haven't really got the whole behaviour worked out.
Step 2 is assign state codes and go through the an implementation technique such as the algorithimic state machine method (ASM) to design and simplify the logic, assuming you are building a logic circuit to implement it. Then you can worry about physical implementation on chips such as field programmable logic sequencers (FLPS), or even FPGA's (field programmable gate arrays), and the representation of the design can either be as a schematic (schematic capture) or a hardware description language (HDL) based.
Don't worry about any of that yet. Just focus on designing the behaviour first.
You've gone straight into a state diagram. That's your end result. That's what you're trying to achieve, so you can then build the state machine.
I think you need to start thinking about using say, a UML sequence diagram to illustrate the behaviour. Each traffic light and sensor (inductive sensor) will be an object on the sequence diagram, and the sensors will trigger a set of behaviour, in a UML sequence diagram time flows down the page, so you can easily represent time based behaviour and what happens to the lights after the inductive sensor has been triggered.
So, I'd suggest design the time based behaviour using a sequence diagram first, then when you've got that right, got what you want, then you can move to a state diagram.
Then you can move to building it.
Best Answer
You could do it with a 555 timer and a counter:
http://www.kpsec.freeuk.com/projects/trafficlight.htm