Background: I plan to use lpmx.5 under cap power but need a way to save the rtc registers to FRAM when the super-cap runs down.
Plan: Use SYSRSTIV SVSH interrupt to wake up and save the counter, or use P5.6 to wake up if the power is restored.
Quote from manual:
The following conditions will cause an exit from LPM4.5:
A wakeup event on an I/O if configured and enabled. The interrupt flag of the corresponding port pin is set (PxIFG). The PMMLPM5IFG bit is set.
A wakeup from the RST pin.
A power-cycle. Either the SVSHIFG or none of the PMMIFGs is set.
Any exit from LPM4.5 causes a BOR. The program execution starts at the address the reset vector points
to. PMMLPM5IFG = 1 indicates a wakeup from LPM4.5, or the System Reset Vector Word register (SYSRSTIV) can be used to decode the reset condition (see the device data sheet).
and
Figure 2-2. Voltage Failure and Resulting PMM Actions not showing the power-down SVSH interrupt.
Revised questions:
- Is the SVSH interrupt available at power-down between SVSH trigger
and BOR reset? - How do I detect a SVSH wake-up?
- If a need IO pin P5.6 wake up – Table 6-10 does not mention PMMLPM5 by name. Is this the LPMx.5 wake-up or $08 vector and is
this the specific one triggered by, say P5.6, if correctly
configured? - Can the SVSH trigger be used to save the RTC counters RTCCNT12 AND RTCCNT34? (see below)
I needed to split question 1 in two parts as I can confirm that SVSH can be used by sampling SYSRSTIV == 0x0E at startup. However, when I read the counters under SVSH they always return zero. I have also confirmed this strange behaviour by triggering SVSH from the active mode.
Is this a hardware bug? I am testing the code with a Rev B chip.
Best Answer
Section 2.2.4 of the User's Guide says:
and: