Electronic – My first project, looking for a review and comments

I agree with much of what Fake said, but some of his points seem to be religious issues with little validity.

1. No, do use net labels. If it can be reasonably done then it's better to connect points directly with lines. However, that's not always possible or reasonable. Obviously it can't be done with multiple sheets, and a messy ratsnest of wires is worse than a few carefully chosen "air wires". Labeling nets is one way to show connections. Everything with the same name is assumed to be connected, and most software will enforce this anyway. Fot that reason it is a good idea to use net labels generated by the software from the name in the database rather than you typing it in. If separate sections of the net ever get disconnected or separately renamed by accident, the software will automatically show this since the name shown comes from the actual net name, not something you type in separately. This is a lot like a variable in a computer language. You know that multiple uses of the variable symbol refer to the same variable.

   Another good reason for net names is short comments. I sometimes name and then show the names of nets only to give a quick idea what the purpose of that net is. For example, seeing that a net is called "5V" or "MISO" could help a lot in understanding the circuit.

2. Yes, show pins of ICs in position relevant to their function, NOT JUST HOW THEY HAPPEN TO BE ON THE CHIP. One important purpose of a schematic is to convey a circuit to others so they can understand it. ICs with pins in physical pin order are difficult to understand. Some people use the excuse that this aids in debugging, but with a little thought you can see that's not true. When you want to look at something with a scope, which question is more common "I want to look at the clock, what pin is that?" or "I want to look at pin 5, what function is that?". In some rare cases you might want to go around a IC and look at all the pins, but the first question is by far more common.

   Physical pin order layouts obfuscate the circuit and make debugging more difficult. Don't do it.

3. Yes, in general it is good to put higher voltages towards the top, lower voltages towards the bottom, and logical flow left to right. That's clearly not possible all the time, but at least a general higher level effort to do this will greatly illuminate the circuit to those reading your schematic.

   This also causes common subcircuits to be drawn similarly most of the time. Once you get more experience looking at schematics, these will pop out at you and you will appreciate this. If stuff is drawn every which way, then these common circuits will look visually different every time and it will take others longer to understand your schematic.

   Good schematics show you the circuit. Bad schematics make you decipher them.

4. Yes, spend some time with placement reducing wire crossings and the like. The recurring theme here is clarity. You should be trying to help people understand the circuit easily, not make them figure it out despite the schematic.

5. No, don't use extra long names. Again, the point is clarity. No names is no information, but lots of long names are clutter, which then decreases clarity. Somewhere in between is a good tradeoff. I don't want to see "8 MHz clock to my PIC", when simply "CLK", "CLOCK", or "8MHZ" would do.

6. No, do use all caps for net names and pin names. Pin names are almost always shown upper case in datasheets and schematics. Various schematic programs, Eagle included, don't even alow for lower case names. One advantage of this, which is also helped when the names aren't too long, is that they stick out in regular text. If you do write real comments in the schematic, always write them in mixed case but make sure to upper case symbol names to make it clear they are symbol names and not part of your narrative. For example, "The input signal TEST1 goes high to turn on Q1, which resets the processor by driving MCLR low.". In this case it is obvious that TEST1, Q1, and MCLR refer to names in the schematic and aren't part of the words you are using in the description.

7. CLEAN UP TEXT PLACEMENT. Schematic programs generally plunk down part names and values based on a generic part definition. This means they often end up in inconvenient places in the schematic when other parts are placed nearby. Fix it. That's part of the job of drawing a schematic. Your schematic above is particularly guilty of this. There are part names and values overlapping all sorts of stuff and are even sideways in a lot of places. Again, the most important point is clarity.

   There is another point in this case. A sloppy schematic shows lack of attention to detail and is a irritation and insult to anyone you ask to look at it. Think about it. It says to others "Your aggrevation with this schematic isn't worth my time to clean it up" which is basically saying "I'm more important than you". That's not a smart thing to say in many cases, like when you are asking for free help here, showing your schematic to a customer, teacher, etc. Neatness and presentation count. A lot. You are judged by your presentation quality every time you present something, whether you think that's how it should be or not. In most cases people won't bother to tell you either. They'll just hire someone else, go on to answer a different question, not look for some good points that might make the grade one notch higher, etc.

1: the capacitor circled in red is optional, that is why there is a jumper link there. According to page 7 in the pin description tables:

"The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND"

Therefore, just use the 100nf cap.

2: AS before, in the pin function table page 8 the COMP pin needs that cap because: "DAC Bias Pin. This pin is used for decoupling the DAC bias voltage"

3: The two blue capacitors on the IOUT pins are usually not loaded, as the schematic suggests "DNI" or "DNL" means do not load (its not normal to have it there). If you had a mostly DC output and there is high frequency noise issues on the output, i guess you could put those there to give a cleaner output.

4: The yellow power supply AVDD and DVDD are indeed power supply decoupling capacitors. You should place these on PCB close to the IC pins associated with those supply rails. C6 and C7 should be placed as close as possible to Pin 2 of the IC. C8 and C9 should be placed as close as possible to Pin 1 of the IC.

5: In the schematic of the datasheet at the end, the one that you have referenced and blocked out some parts - there is a clock generator IC, or an optional CLK input pin. This means the chip doesnt actually have a proper crystal driver inside. You cannot therefore give it a crystal with load caps (usually in the 18-33pF range) because it cannot drive the signal itself. You must supply it with an externally generated clock signal. Description for Pin 5 (MCLK) is as follows:

"Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock."

So you must give it a proper clock, not a crystal (analog style clock i supposed you could consider a crystal)

6: good luck mate! Following the evaluation board schematic is a safe bet. Any other questions, don't hesitate to ask.