I would like to get some ideas for my problem. I have a HW which has a main processing unit (Beaglebone, host controller) which is connected to four galvanically seperated STM32 microcontrollers. All of the STM32 microcontrollers are doing analog measurement with the same sampling frequency (100ksps). The STM32 mcus are doing the acquisition and the Beaglebone collects the data over SPI and evaluates it. The acqusition is started on all of the microcontrollers almost the same time. I would like to run the measurements over multiple hours. All STM32 has a 16MHz external crystal for clock source, with PLL the core is running at 100MHz. But because the crystals have tolerance the sample points will be shifted between the stm32 microcontrollers. After some minutes the differences are significant. It would be nice if the delay between the microcontrollers would be between +-10us – 100us.
The acquisition is continuous. I do not want to miss any samples.
Question 1: is there a method to do sampling correction/syncronization between the microcontrollers? Can you suggest a literature in this topic?
Question 2: if hardware redesign is possible, currently I am thinking in software solution, how can I put syncronization between the seperated microcontrollers?
Remark:
what if the main processing unit measures somehow the delay between the microcontrolers. Then it sends a number to each of the microcontroller about how much is the difference referenced to an ideal frequency (sampling frequency or the operation frequency of the host). And then each microcontroller would change the sampling frequency a bit (100.1ksps or 99.9ksps). Something like this is in my mind. Can this work? Did anyone do something before?
Every comment are welcomed!
Best Answer
Both of these work on the idea that there is at least some delay in the sample loop of the slaves, which could be adjusted to make the slowest slave catch up with the fastest. That is, that there's a software timer which triggers an individual capture of the ADC.
Pure software You could read about the Network Time Protocol, and borrow/adapt as much of it as you thought necessary. At base, a master sends out time signals and the slaves calibrate themselves by a (software) phase-locked loop. With dedicated microprocessors and SPI communications, those mechanisms should get your your accuracy.
Explanation of NTP mechanisms Documentation, Presentation. NTP has quite a number of modes. The ones which might have mechanisms you can borrow are making the control host a fake reference clock (deemed to be correct) and having the slaves work like broadcast clients (even if they are receiving the messages one at a time). The main thing to read about is the clock discipline algorithm, which explains how the client gets its clock in sync with the master.
I'd consider using one of the STM32s as a clock master, and the host controller gets a nominal time from that, rather than using the host controller's clock. This is because we're not trying to sync the slaves to the real time, we're trying to remove time skew from the multiple samples. (As far as I've understood your goal.)
If you find you want to do it according to standards, NTP is defined as an internet RFC 5905, though you might want to also read the earlier versions which are a bit simpler. You might also want to look at PTP (precision time protocol), which is an IEEE standard IEEE Std 1588-2002. It's much more accurate, also much more complex, and much more expensive!
At the higher end of your resolution (0.1 ms), it should be entirely possible to simply get the host to tell each slave periodically "the time is X ns", and leave them to sample on X % 10000 = 0. All the jitter will be in the host controller. Assuming Linux kernel, you'll need to read
clock_gettime(3)and pay attention toCLOCK_MONOTONICor perhapsCLOCK_MONOTONIC_RAWsettings.) The only thing to fret about is how to deal with a slave smooths the changing of its clock so it doesn't miss any sampling: I'd guess you can just sample "right now" if you have to jump. It depends on how much spare time the slaves have between samples.Hardware If you can afford a wire and an input on the slaves (and the additional isolation), run an extra wire to tell all the slaves to sample. If that generates interrupts on the slaves, they will be about as synced as it's possible to get in software, and could be much better than your target. The optimal syncrhonisation (given in Jeroen3's answer), is to trigger the ADC capture directly from an IO pin.