modenmossaturation
I have a question about the saturation mode. The cross-section of an NMOS transistor in saturation mode is usually drawn like this:
But it seems to me that there can be no current from source to drain in this case (because there is no contact between the channel and the drain). From the diagram that plots V_DS against I_D, it can be seen that in saturation mode, there is a current (it just doesn't increase when we increase V_DS).
So what is going on in saturation mode?
First, there are diodes b/w source and drain leading to the substrate. In an NMOS they are 99.9% of the time tied to the most negative voltage, and for PMOS the most positive voltage. This prevents them from ever turning on unless somehow some signal exceeds the rails.
So you would have a hard time getting this system to work, because to turn off the FET you would need to raise the body voltage (like a PMOS). But, you can't rise it more than the forward voltage of the diodes or you would burn the device.
You would need a very small threshold voltage for the FET and a very large Vf of the diode to even consider this to work. But then there are other problems as well:
You turned a capacitive gate load to drive into a resistive/capacitive (with SIGNIFICANTLY more cap) load.
I would expect this to also be significantly slower.
Frankly, the most telling thing, should be that no one does do this. NMOS only logic was pretty common 20-30 years ago. Here the loads were typically just resistors, so the gates burned a lot of static power. They tried all sorts of tricks until PMOS finally came around, but afaik it was never to use an NMOS like that.
EDIT In one of your comments you mentioned you were tying the source to the body. In this case, if you have the gate at a biased voltage, you are pretty much describing a common gate amplifier. In this case you are safe. I misunderstood your usage in the initial response:
Your understanding is correct.
For circuit design the source is usually the reference terminal. Consequently so called source-referenced transistor models were introduced to formulate the drain current as a function of voltages relative to the source terminal (\$V_{GS}, V_{DS} V_{BS}\$). In cases where the bulk source voltage \$V_{BS}\$ is zero the gate-source voltage \$V_{GS}\$ is equal to the gate-bulk voltage, so we actually see the effect of the gate-bulk voltage \$V_{GB}\$. For non-zero \$V_{BS}\$ the body-effect is used to model the behavior of the transistor. The body-effect describes a change of the threshold voltage \$V_T\$ and so the behavior of the transistor depending on \$V_{GB}\$ is obtained.
The threshold voltage \$V_T\$ with a backgate-bias voltage \$V_{SB}\$ is given by the following expression (see Wikipedia). $$ V_T = V_{T0} + \gamma\left(\sqrt{|-2\phi_F + V_{SB}|}-\sqrt{|2\phi_F|} \right) $$ where \$V_{T0}\$ is the threshold voltage for \$V_{BS} = 0\$, \$\gamma\$ is the body-effect parameter and \$2\phi_F\$ is the surface-potential.
Integrated MOS transistors are often symmetric. Therefore the source and drain terminals are not defined by the layout of the transistor but only by the applied voltages. In order to get equations that reflect that symmetry body-referenced models are used, where indeed voltages are referred to the substrate and not the source of the transistor.
Best Answer
At onset of saturation, inversion charge near drain decreases until it becomes zero, close to drain region. VD at which this happens is called pinchoff and drain current starts to saturate. At saturation regime (VD > VD-sat), pinchoff moves towards source leaving behind a depleted region; inversion charge drifts down conducting channel and is then injected into depletion region. ID will essentially remain constant because inside channel potential is fixed at VD-sat.
Please note that this is kind of "first-order" behavior of the MOS transistor, in reality the drain current in saturation regime is not constant and is affected by many other phenomena e.g. channel length modulation, velocity saturation, etc.