Electronic – NMOS – Why is a resistor necessary

First with the FET switched on. The on-resistance of a FET can be very low, even as low as a few mΩs for high current ones, but let's take an average FET with a 1 Ω on-resistance, and a 10 kΩ pull-up resistor. Let's say \$V_S\$ = 5 V. The FET pulls the output level almost to ground; it forms a resistor divider with R, so that

\$ V_{OUT} = \dfrac{R_{DS(ON)}}{R + R_{DS(ON)}} V_S = \dfrac{1 \Omega}{10000 \Omega + 1 \Omega} 5 V = 0.5 mV \$

So with the FET on we have as good as zero.

Next with the FET off. Then there's no current through R, and since the voltage across R = R \$\times\$ current (Ohm's Law) the voltage is also zero. If \$V_S\$ is 5 V, and there's no voltage difference across R, then \$V_{OUT}\$ also must be 5 V.

Just like the FET isn't a perfect switch when closed it isn't a perfect switch when open either. There's a small leakage current, say up to 1 µA. That will cause (again due to Ohm) a voltage drop of 1 µA \$\times\$ 10 kΩ = 10 mV across the resistor, and the output will be 4.99 V instead of 5 V. The leakage current is the reason why you shouldn't choose R too high. If R would be 1 MΩ then the voltage drop would be 1 V and that may be too much.

So it works with the resistor. What if we omit it? With the FET on the output woill be drawn to ground, but with the FET off the output would be floating if our FET was a perfect switch, so it would be undefined. With the leakage current it might still pull the output low, if the input impedance of the load was very high. So the resistor is needed to define the level when the FET is off.

The Vth of a NMOS is the Vgs at which it operate until (ie. so long as Vgs > Vth it will continue to conduct).

As you have stated this Vth is 1.0V. Initially when the switch is closed the NMOSes will turn on as the voltage at their respective sources will be zero and the voltage at the gates will be 2.5 - this is well above the Vth that you mentioned of 1.0V. As the capacitor charges through these NMOSes which are now more or less making short circuit the voltage at the source is increasing and it will continue to do this until it reaches 1.5V at which point the Vgs will start to go below 1.0V thus making the NMOS transistors turn off.

The fact that there are two of them doesn't really make any difference, there could be 1 or 10 and it would have the same result.

The mistake you made by thinking it will only charge to 0.5V is that the voltage drop is not from the drain - source so there would not be two drops, it si only to do with the potential between the gate and source and as explained once this goes below 1.0V the transistor turns off.