Electronic – NMOS: why VGS instead of VG

Wiki says...

In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices are used as load "resistors" in logic circuits (in depletion-load NMOS logic, for example). For N-type depletion-load devices, the threshold voltage might be about –3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS). In PMOS, the polarities are reversed.

So for a depletion-mode PMOS it is normally ON at Zero volts but you need 3V or more on the gate higher than the supply voltage to turn OFF. Where do you get that voltage? I think , that's why it is uncommon.

In practise now we call them High Side Switches or Low Side switches for power MOSFETs. They prefer not to combine enhancement and depletion mode in the same chip as the processing costs are almost double. This patent defines some innovation and better physical desc. than I can remember. http://www.google.com/patents/US20100044796

It is possible though what you are suggesting and performance are key issues. However when it comes down to low ESR, MOSFETS are like voltage controlled switches with ESR changing over a wide range of DC voltages unlike bipolar transistors which are 0.6 to < 2V for max peak in some case. Also for MOSFETs it is constructive to think of them as having an impedance gain of 50 to 100 when looking at loads and ESR of source. So consider you need a 100 ohm source to drive 1 ohm MOSFET and 10 ohm source to drive a 10mΩ MOSFET if you use 100:1, Conservative is 50:1. This is ONLY important during the transition period of the switch, not the steady state gate current.

Whereas bipolar hFE drops dramatically so you consider hFe of 10 to 20 good when saturated for a power switch.

Also consider that MOSFETS as charge-controlled switches during transition, so you want to have a big charge available to drive the gate capacitance and load reflected into gate with a low ESR gate drive, if you to make a fast transition and avoid commutation ringing or bridge cross-over shorts. But that depends on design needs.

Hope that isn't too much info and the patent explains how it works for all modes of P N type depletion and enhancement in terms of device physics.

The Vth of a NMOS is the Vgs at which it operate until (ie. so long as Vgs > Vth it will continue to conduct).

As you have stated this Vth is 1.0V. Initially when the switch is closed the NMOSes will turn on as the voltage at their respective sources will be zero and the voltage at the gates will be 2.5 - this is well above the Vth that you mentioned of 1.0V. As the capacitor charges through these NMOSes which are now more or less making short circuit the voltage at the source is increasing and it will continue to do this until it reaches 1.5V at which point the Vgs will start to go below 1.0V thus making the NMOS transistors turn off.

The fact that there are two of them doesn't really make any difference, there could be 1 or 10 and it would have the same result.

The mistake you made by thinking it will only charge to 0.5V is that the voltage drop is not from the drain - source so there would not be two drops, it si only to do with the potential between the gate and source and as explained once this goes below 1.0V the transistor turns off.